Hi,
I came across one scenario where i want to finish my simulation by killing or stopping all the running sequences.
Here is the scenario,
From the UVM test i called two sequences to run on the two different sequencers, now these two sequences are started running in parallel on two different sequencers.
seq1: Let’s say driving some data continuously, it’s like never ending or long process.
seq2: This is to verify the functionality a module.
Now after some time seq2 execution was completed and simulation is still going on as seq1 is running .
In this situation how to stop or end the seq2 to end the simulation or testcase execution.
Is there any way in UVM to do this.
Can anyone give an idea how to achieve this.
In reply to srikanth_m:
Hi,
class seq1 extends uvm_sequence #(uvm_seq_item seq_item);
bit kill_seq;
//body method
fork
begin
//drive data continuously
end
begin
wait(kill_seq);
kill_seq = 0;
end
join_any
disable fork;
endclass
Now in testlevel the part where you will have the sequence running:
fork
begin
seq1.start(seqr1);
end
begin
seq2.start(seqr2);
seq1.kill_seq = 1;
end
join
I think this approach meets your requirement
In reply to srikanth_m:
Hi,
It can be achieved using fork … join_any and disable fork constructs.
Inside virtual sequence body part…
task body ();
...
fork
seq1.start(seqr1,this);
seq2.start(seqr2,this)
join_any
disable fork;
...
endtask
**OR**
Inside tescase run_phase/main_phase ....
task run_phase (uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
...
fork
seq1.start(seqr1,this);
seq2.start(seqr2,this)
join_any
disable fork;
...
phase.drop_objection(this);
endtask
In reply to avpchandra:
Hi,
I am calling the sequences from testcase itself not from the another sequence.
I don’t think we use fork join in testcase level, we use it sequence.
However, your code works even without kill bit like
fork
begin
seq1.start(seqr1);
end
begin
seq2.start(seqr2);
// seq1.kill_seq = 1;
end
join_any
But, i want to know if any possible way to end the sequence without any dependency.
Something like $finish in verilog/system verilog.
Thanks.
In reply to srikanth_m:
For this requirement you can consider
$finish = fork … join_any + disable fork :)
OR
if anyhow sequence2 completion time is known,+UVM_TIMEOUT simulation argument can be used to terminate simulation after specified time.
In reply to srikanth_m:
Hi Srikanth,
whatever code i have given in that upper part is seq1’s body method pseudo-code which has parallel thread of kill_seq.
In test level run_phase()
task run_phse(uvm_phase phase);
super.run_phase(phase);
fork
begin
seq1.start(seqr1);
end
begin
seq2.start(seqr2);
seq1.kill_seq = 1;
end
join
endtask
NOTE: If you use join_any directly in the testcase there might be a problem that if seq1 completes early then it will come out of fork and disables it. Is that fine as per your requirement?
In reply to srikanth_m:
UVM is providing you anything for all your topics! Why do you want to stop the sequence? If I understood you right there is no reason for this.
What I’d do in your case is to stop the processing of sequence items in the driver which belongs to seq1. This stops automatically the generation of sequences.
In reply to chr_sue:
Hi,
Thanks for your reply.
Here, as i started the two sequences from testcase itself by using config_db-set(), i want to finish the first sequence. otherwise my simulation will run for long time/forever.
For this reason i want to stop the seq1.
I hope you understand my scenario.
In reply to srikanth_m:
Hi Srikanth,
can you tell me how you are stating the sequence through config db?
Whether you have raised objections inside the sequence or not? especially for seq1?
In reply to avpchandra:
This is how i am starting the sequences on different sequencers
uvm_config_db#(uvm_object_wrapper)::set(this,“top_tb0.vir_sqr.run_phase”,“default_sequence”, seq_1::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,“top_tb0.vir_sqr.sqr2.main_phase”,“default_sequence”, seq_2::type_id::get());
No objections raised in seq1, in sequence one i have loop which takes long to complete. But after seq2 exe completes i don’t need seq1 to run.
Actually seq1 is driving some data for me to verify some functionality which i am doing in seq2.
Have some issues with seq2 as it is from VIP and VIP sequences are calling other sequences internally and pointing to p_sequencer.other_sqr. So, i have to run that sequence directly on seq2. otherwise i will get fatal errors related to other_sqr.
In reply to srikanth_m:
I guess you did not understand my idea. If you stop the processing of sequence items in your drivers the sequence gexecution stops, because the get/get_next_item is blocking.
This is independent how you are starting your sequences (automatically or manually).
In reply to chr_sue:
I am calling UVC sequence from my seq1 and that creates the item.
so, the calling the UVC sequence is continuous process. because of this seq1 is running.
Here, i just want to know if UVM provides any way to terminate the sequence execution.
In reply to srikanth_m:
What you are saying is not true. But if you are insisting on killing the sequence you can use one of the synchronization mechanism UVM is offering. I do not know all your details, but I could imagine to use either a uvm_:event or uvm_barrier.
In reply to srikanth_m:
Hi,
Instead of registering default sequence via uvm_object_wrapper use sequence object. Refer below code.
uvm_config_db#(uvm_sequence_base)::set(this,"top_tb0.vir_sqr.run_phase","default_sequence", seq_1_h);
uvm_config_db#(uvm_sequence_base)::set(this,"top_tb0.vir_sqr.sqr2.main_phase","default_sequence", seq_2_h);
Now in testcase’s run phase you can monitor state of seq2 and kill seq1.
task run_phase (uvm_phase phase);
seq_2_h.wait_for_sequence_state(UVM_FINISHED); // wait for seq2 to be finished
seq_1_h.kill(); // kill sequence 1
endtask : run_phase
Make sure that seq1 is not raising any objection before kill, otherwise simulation won’t be completed due to raise and drop objection count miss match.
In reply to kerulmodi:
Hi kerulmodi,
Thanks, Something like this only i am expecting.
Also used the below method to drop the raised objections and killed the sequence, if any pending objections sequence is not getting killed.
https://verificationacademy.com/forums/uvm/how-drop-all-raised-objection
In reply to srikanth_m:
There is another thread in verification academy that discuse the stop_sequence() function.
The stop_sequence() function does what you want. You can call that function from a sequencer handler that runs (or has run see link below) a sequence transaction.
The following article explains how it works and the possible problems of using it
https://verificationacademy.com/forums/uvm/leaf-level-sequencers-stopsequences-terminating-virtual-sequence-which-running-virtual-sequencer