I’m trying to implement a simple agent package and referring with Package/Organization | Verification Academy
There is an agent package implementation as the below. But especially, I couldn’t understand about handling a sequencer.
My agent also has a sequencer, but I should not include it in my agent package by following the instructions below.
//Create a typedef for the mem_sequencer since the uvm_sequencer class should not be extended
typedef uvm_sequencer #(mem_item) mem_sequencer;
I’m confused that if I just declared the typedef of my sequencer in the agent package, how should I handle my sequencer in my uvm testbench?
/*
* This package contains all of the components, transactions
* and sequences related to the mem_agent. Import this
* package if you need to use the mem_agent anywhere.
*/
package mem_agent_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
//Typedef used by the mem_agent
typedef enum bit[1:0] {READ, WRITE, PAUSE} instruction_type;
//Include the sequence_items (transactions)
`include "mem_item.svh"
//Include the agent config object
`include "mem_config.svh"
//Include the components
`include "mem_driver.svh"
`include "mem_monitor.svh"
//Create a typedef for the mem_sequencer since the
// uvm_sequencer class should not be extended
typedef uvm_sequencer #(mem_item) mem_sequencer;
`include "mem_trans_recorder.svh"
`include "mem_agent.svh"
//Include the API sequences
`include "mem_seq_base.svh"
`include "mem_read.svh"
`include "mem_write.svh"
endpackage : mem_agent_pkg