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-how to run a uvm_sequence_library from a virtual sequence??

pratyaksha navalkar
pratyaksha navalkar
Full Access
6 posts

Hello,

Scenario
1. I have two UVCs driving the DUT. host and top
2. I am using virtual sequence to run the sequences of host and top
3. I have created a host_seq_lib of type host_sequence_library.
4. I want to randomly execute any of the sequences from the sequence library until a signal rises.

Problem :

I try to run host_seq_lib in my virtual sequence like this.

class rcc_full_flag_seq extends uvm_sequence;

	// provide the implementations of virtual methods like get_type()
	`uvm_object_utils(rcc_full_flag_seq)
	`uvm_declare_p_sequencer(badge_vsequencer)

	// top de-assert reset sequence
	top_ctrl_disable_reset_seq top_disable_reset;
	top_ctrl_enable_reset_seq top_enable_reset;

	host_seq_lib	host_seqs;
   host_config cfg;

	// new constructor
	function new(string name="rcc_full_flag_seq");
		super.new(name);
	endfunction : new	

   virtual task pre_body();
		// Get the configuration object
		if(!uvm_config_db #(host_config)::get(null, get_full_name(), "host", host_cfg)) begin
	    `uvm_error("HOST_CFG", "host_config not found");
		end
		host_seqs.selection_mode = UVM_SEQ_LIB_RANDC;
		host_seqs.min_random_count = 15;
		host_seqs.max_random_count = 30;
	endtask

	virtual task body();
			`uvm_do_on(top_disable_reset, p_sequencer.top_ctrl_seqr)
			fork
			repeat(30);
			begin		
				`uvm_do_on(host_seqs, p_sequencer.host_seqr)
			end
			host_cfg.wait_for_full_rise();
			join_any
	endtask
endclass

HOwever I get an error
* Fatal: (vsim-131) /home/prra/trunk/badgeComponent/uvm_testbench/rccgpu_tb/tb/badge_virtual_seqs.sv(53): Null instance encountered when dereferencing '/badge_tb_top/rcc_full_flag_seq::pre_body/this*.host_seqs

Question - Can I run a sequence library inside a virtual_sequence??

Answers

pratyaksha navalkar
pratyaksha navalkar
Full Access
6 posts

Hi,

Any replies???

dave_59
dave_59
Forum Moderator
1474 posts

Where did you construct your sequence library host_seq?

We do not recommend using sequence libraries. It is much easier to use a simple array. See http://verificationacademy.com/uvm-ovm/Sequences/Generation

Comments on this answer

Hi,

I constructed the sequence library of host in host_seq_lib.sv file.

I idea of having a uvm_sequence_library was to randomly run any of the sequences from the library in a test.
To restrict the randomization only to few sequences, I make a library of it call it in the test.

How do I accomplish this without library. uvm_sequence_library seemed the most obvious way to do it. But it does not work with virtual_sequences..

If I have mis-understood, please correct.
Why mentor does not recommend uvm_sequence_library when such class is available in -uvm??? Please advice

Thanks,
Pratyaksha