How to reuse the bfm tasks written at DUT level during SOC integration?

UVM
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1

I have been trying to find out if there is any example of reusing bfm tasks written at dut level during the SOC validation ?

**Scenario:
**
I have 2 duts and each of them have their own interface. Some of the signals are shared at SOC level. I have written BFM tasks at DUT level to drive them. Now I want to reuse the same tasks and tests. Problem is “Some of the signals are shared at SOC level and that shared signal gets driven by multiple drivers”

i.e, When I run first bfm task ==> it tries to drive that ifc signal.
then I call other task in the second dut bfm which again tries to drive same signal.

is there anything wrong in my approach ? I would like to reuse my bfms and sequences. Some please point me to example code which shows Integration validation ?

2

In reply to Varunshivashankar:

See my DVCon paper The Missing Link: The Testbench to DUT Connection

As well as

https://verificationacademy.com/content/re-ovm-wrapper-verilog-bfms-9