I am trying to flush the uvm_tlm_analysis_fifo whenever input is reset. I have tried uvm_tlm_analysis_fifo.flush() but it didnt flush the fifo …
In reply to ejaz_parvez:
Could you please some more code, especially how you propagate the reset to the TLM world.
I have been trying to flush the fifo in env by using this code.
include "fifo_agent.sv" include “fifo_scoreboard.sv”
class my_environment extends uvm_env;
`uvm_component_utils(my_environment);
virtual dut_if dut2env;
my_agent_1 agent_1_h;
my_agent_2 agent_2_h;
my_scoreboard scoreboard_h;
uvm_tlm_fifo #(fifo_seq_item) agt_1_scb_fifo;
uvm_tlm_fifo #(fifo_seq_item) agt_2_scb_fifo;
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
if(!uvm_config_db#(virtual dut_if)::get(this,“”,“dut_if”,dut2env))
`uvm_fatal(“NO_VIF”,{“virtual interface must be set for:”,get_full_name(),“.vif”});
agent_1_h = my_agent_1::type_id::create(“agent_1_h”, this);
agent_2_h = my_agent_2::type_id::create(“agent_2_h”, this);
scoreboard_h = my_scoreboard::type_id::create(“scoreboard_h”, this);
agt_1_scb_fifo = new(“agt_1_scb_fifo”, this, 0);
agt_2_scb_fifo = new(“agt_2_scb_fifo”, this, 0);
endfunction
function void connect_phase(uvm_phase phase);
agent_1_h.ap.connect(agt_1_scb_fifo.blocking_put_export);
agent_2_h.ap.connect(agt_2_scb_fifo.blocking_put_export);
scoreboard_h.exp_port.connect(agt_1_scb_fifo.blocking_get_export);
scoreboard_h.act_port.connect(agt_2_scb_fifo.blocking_get_export);
endfunction
task run_phase(uvm_phase phase);
begin
reset();
end
endtask
task reset();
if(dut2env.reset) begin
agt_1_scb_fifo.flush();
agt_2_scb_fifo.flush();
$display(“reset work”);
end
endtask
endclass : my_environment
this is the code of scoreboard which i am using:
task run_phase(uvm_phase phase);
repeat(400)
begin
exp_port.get(tr_exp);
act_port.get(tr_act);
result = tr_exp.compare(tr_act);
if (result)
$display("Compare SUCCESSFULLY");
else if(!result)begin
`uvm_error("WARNING", "Compare FAILED")
$display("The expected data is");
tr_exp.print();
$display("The actual data is");
tr_act.print();
end
end
endtask
In reply to ejaz_parvez:
I guess your scoreboard is still compairing. Right?
I do not know your monitor code, but you should consider the scoreboard is working on the TL.
The monitor might be just working and sending a transaction to the analysis port, before the reset becomes active. Using the reset signal in the env and other TL components is not a good idea.
yes,the scoreboard is still comparing ,everything is working well,until when my reset gets high. basically i tried to flush the data stored in tlm fifo when reset gets high …but as it couldnt flush the data .my scoreboard shows comparison failed as the datain stored before the reset gets high is not flushed.Thus,it mainly compared the datain before reset with the data out of my dut.
Moreover could you tell me where to use this reset signal
In reply to ejaz_parvez:
Your fifo gets flushed, but to early. After the flush it gets new data from the monitor.
Could you please show your monitor code?
this is the monitor code
class my_monitor_1 extends uvm_monitor;
`uvm_component_utils(my_monitor_1)
virtual dut_if dut2monitor1;
uvm_blocking_put_port #(fifo_seq_item) ap;
fifo_seq_item tr;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
ap = new(“monitor_1_ap”, this);
if (!uvm_config_db #(virtual dut_if)::get(this, “”, “dut_if”, dut2monitor1))
`uvm_fatal(“NODUT_IF”,{“virtual interface must be set for:”,get_full_name(),“.dut_if”});
endfunction
task run_phase(uvm_phase phase);
repeat(400)
begin
@(posedge dut2monitor1.clk)
tr = fifo_seq_item::type_id::create(“tr”);
if (!dut2monitor1.reset & !dut2monitor1.fifo_full & dut2monitor1.wre)
begin
tr.datain = dut2monitor1.datain;
ap.put(tr);
end
end
endtask
endclass : my_monitor_1
// read monitor
class my_monitor_2 extends uvm_monitor;
`uvm_component_utils(my_monitor_2)
virtual dut_if dut2monitor2;
uvm_blocking_put_port #(fifo_seq_item) ap;
fifo_seq_item tr;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
ap = new(“monitor_2_ap”, this);
if (!uvm_config_db #(virtual dut_if)::get(this, " “,“dut_if”, dut2monitor2))
`uvm_fatal(“NODUTIF”,{“virtual interface must be set for:”,get_full_name(),”.dut_if"});
endfunction
task run_phase(uvm_phase phase);
repeat(400)
begin
@(posedge dut2monitor2.clk)
tr = fifo_seq_item::type_id::create(“tr”);
if (!dut2monitor2.reset & !dut2monitor2.fifo_empty & dut2monitor2.rde)
begin
#1
tr.datain = dut2monitor2.dataout;
ap.put(tr);
end
end
endtask
endclass : my_monitor_2
In reply to ejaz_parvez:
I believe the reset is not working correctly in your monitor code. You are synchronizing always on your clock. At that time the signals will be sampled. And the reset is there inactive.
BTW use the uvm_analysis_port in the monitor. A blocking port in the monitor causes problems.
Could you share your code with me privately?
If yes, here is my email:
christoph@christoph-suehnel.de
i have also tried analysis port in monitor but it doesn’t work out.ok i will share my code with you.
i mailed you the code.if you could figure out my problem please reply me.
In reply to ejaz_parvez:
Please see your email.
Something happened with my email from the weekend.
Can you please tell me if you received the code.
In reply to chr_sue:
In reply to ejaz_parvez:
Please see your email.
Something happened with my email from the weekend.
Can you please tell me if you received the code.
I didn’t get your mail.