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  • How to rerun long running tests efficiently in UVM/System verilog?

How to rerun long running tests efficiently in UVM/System verilog?

UVM 7028
#uvm 282 #systemverilog 109 Advanced Verification 3
Venkateshwara Rao
Venkateshwara Rao
Full Access
9 posts
December 18, 2018 at 2:00 am

Lets say i have a long running test which runs for days. In a scenario, i found a UVM error after 30 hours of simulation. I have further several errors reported too. I have fixed the first error and I want to quickly check that the fix is working or not.
Is there any way to re-run the test ( might be any enhancements needed in testbench) by not wasting 30 hours.
Please suggest any changes in testbench to make this kind of debug easier.

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chr_sue
chr_sue
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4032 posts
December 18, 2018 at 2:20 am

In reply to Venkateshwara Rao:
Your simulator should provide this functionality.
But you should ask yourself if it is efficient to run such a test. Why not splitting this test in smaller pieces?

dave_59
dave_59
Forum Moderator
11444 posts
December 18, 2018 at 7:44 am

In reply to Venkateshwara Rao:

Can't answer this question without knowing anything about why this test runs for days, and what the reason was for the error.

Also, for any test that runs for more than one day, you should spend some time profiling the simulation to see why it is taking so long. Sometimes changing a few lines can give you 2-3x performance improvement.

— Dave Rich, Verification Architect, Siemens EDA

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