Since I cannot use hierarchical references in my UVM components (as the components are declared in packages), I am trying to store a hierarchical reference (to an internal register map of the DUT) inside the uvm_config_db and get it in my UVM component.
Having said that, I am finding it difficult to know what type to use in the set command:
as the register map is declared with a special user typedef inside a VHDL package even though it is just an array.
For instance, I can access the register map in my top using the code:
logic [31:0] reg_val = DUT.model.register_map.reg_array.value;
But when I want to pass access of the whole register map to a UVM component (via uvm_config_db) I do not know what type I should use in the uvm_config_db #( ). Putting the actual type as declared in the VHDL doesn't work because the type is declared inside a VHDL package and I am using vlog to compile this systemverilog code so it can't see the type declaration. So perhaps this question is more about getting visibility to the typedef declaration (located inside a VHDL package) from a SystemVerilog file? (If that is the way to solve this problem...?)