How to reference internal user typedef of VHDL DUT?

Question

Since I cannot use hierarchical references in my UVM components (as the components are declared in packages), I am trying to store a hierarchical reference (to an internal register map of the DUT) inside the uvm_config_db and get it in my UVM component.

Having said that, I am finding it difficult to know what type to use in the set command:

uvm_config_db #(WHAT_TYPE??)::set(null,"*",WHAT_STRING,DUT.model.register_map.reg_array);

as the register map is declared with a special user typedef inside a VHDL package even though it is just an array.

For instance, I can access the register map in my top using the code:

logic [31:0] reg_val = DUT.model.register_map.reg_array[0].value;

But when I want to pass access of the whole register map to a UVM component (via uvm_config_db) I do not know what type I should use in the uvm_config_db #( ). Putting the actual type as declared in the VHDL doesn't work because the type is declared inside a VHDL package and I am using vlog to compile this systemverilog code so it can't see the type declaration. So perhaps this question is more about getting visibility to the typedef declaration (located inside a VHDL package) from a SystemVerilog file? (If that is the way to solve this problem...?)

Answer 1

Solution

S.P.Rajkumar.V

Full Access

118 posts

January 12, 2018 at 4:52 pm

Is your intention to observe DUT register value do decide your sequence in the driver/monitor?
I am not sure why you want to pass the register map through config_db. If you want to have access then UVM RAL is the way to go.

But if RAL is not set up for you, and you quickly want to access a couple of registers, you can use the interface approach.
1) Add those registers in the interface,
2) do the necessary connections using 'assign' at the top tb. (given that you take care of VHDL datatype (register type) conversion to logic/reg [31:0])
3) pass on the interface to the UVM_Component through uvm_config_db::set, so the component can retrieve it and can reads the register value.

Answer 2

chr_sue

Full Access

2825 posts

January 13, 2018 at 7:50 am

In reply to ce_2015:

Quote:

Since I cannot use hierarchical references in my UVM components (as the components are declared in packages), I am trying to store a hierarchical reference (to an internal register map of the DUT) inside the uvm_config_db and get it in my UVM component

For me it is completely unclear what your intention is. If you are using the register layer you do not need what you are intending, because the register value you want to observe is in te register mirror in your UVM testbench.

Answer 3

ce_2015

Full Access

39 posts

January 16, 2018 at 5:43 am

In reply to S.P.Rajkumar.V:

Quote:

Is your intention to observe DUT register value do decide your sequence in the driver/monitor?
I am not sure why you want to pass the register map through config_db. If you want to have access then UVM RAL is the way to go.
But if RAL is not set up for you, and you quickly want to access a couple of registers, you can use the interface approach.
1) Add those registers in the interface,
2) do the necessary connections using 'assign' at the top tb. (given that you take care of VHDL datatype (register type) conversion to logic/reg [31:0])
3) pass on the interface to the UVM_Component through uvm_config_db::set, so the component can retrieve it and can reads the register value.

My intention is only to use the "mirror" approach in a Scoreboard to periodically compare a separately allocated regmap variable in the Scoreboard to the actual regmap in the DUT. I don't intend for the Driver or sequencer to care do anything based on these regs. I don't have access to RAL.

Quote:

For me it is completely unclear what your intention is. If you are using the register layer you do not need what you are intending, because the register value you want to observe is in te register mirror in your UVM testbench.

I'm not using the Register Layer. I am making a "shadow register copy" in my Scoreboard that is compared with the actual registers from time to time. That is all.

The disconnect for me is how do I give the Scoreboard visibility to the VHDL's regmap (which is declared as a user typedef. The uvm_config_db seems like the recommended method since hierarchical references are discouraged/not allowed from inside packages.

Answer 4

chr_sue

Full Access

2825 posts

January 16, 2018 at 6:27 am

In reply to ce_2015:

There are 2 Problems:
(1) any typedef you are using in VHDL you can make available especially using Questa in SV using the corresponding switch (-mixedsvvh) during compilation.
(2) VHDL until VHDL-2008 is not transparent from outside, i.e. it is forbidden/impossible to use a hierarchical Path from SV/UVM.

This is one of the reasons why there is the RAL in UVM.

Answer 5

ce_2015

Full Access

39 posts

January 16, 2018 at 6:52 am

In reply to chr_sue:

I suppose then my issue trying to figure out (1). For (2), the VHDL is compiled as VHDL-2008 and I can confirm that my top.sv can reference VHDL internals (it's just getting UVM components to reference them).

Anyways back to (1), I am trying to compile the VHDL package along with my SV structure that contains the typedef using this syntax:

vlog -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

where "tb.f" contains the testbench files and "proj_pkg.vhd" contains the VHDL typedef of the regmap.

However, I am getting errors saying that it could not find the proj_pkg that I reference in my top:

import proj_pkg::*;

I am using Questasim.

Answer 6

chr_sue

Full Access

2825 posts

January 16, 2018 at 7:53 am

In reply to ce_2015:
I do not believe this Working. It should give you a compile errror:

vlog -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

Use instead
vcom -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

Answer 7

ce_2015

Full Access

39 posts

January 16, 2018 at 10:03 am

In reply to chr_sue:

Quote:

In reply to ce_2015:
I do not believe this Working. It should give you a compile errror:
vlog -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

Use instead
vcom -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

Thank you for the recommendation. However, what you provided isn't working either... Out of curiosity, why do you recommend using vcom instead of vlog where all of the files listed in tb.f are SystemVerilog files?

The error I get now is:

Error: (vcom-1995) Package "proj_pkg" cannot be imported in SystemVerilog designs.

I should add that the code I am using to import the package inside top is:

module top;
   import   proj_pkg::*;
   user_type_regmap register_map;
   ...
endmodule

There may be a need to also include the VHD package file inside the top? This leads to other errors though so I am not certain...

Answer 8

ce_2015

Full Access

39 posts

January 16, 2018 at 10:25 am

In reply to S.P.Rajkumar.V:

Quote:

Is your intention to observe DUT register value do decide your sequence in the driver/monitor?
I am not sure why you want to pass the register map through config_db. If you want to have access then UVM RAL is the way to go.
But if RAL is not set up for you, and you quickly want to access a couple of registers, you can use the interface approach.
1) Add those registers in the interface,
2) do the necessary connections using 'assign' at the top tb. (given that you take care of VHDL datatype (register type) conversion to logic/reg [31:0])
3) pass on the interface to the UVM_Component through uvm_config_db::set, so the component can retrieve it and can reads the register value.

Back to this recommendation, my original problem surfaces again with the interface approach. My issue is getting the typedef visibility from the VHDL package into the interface. Because the regmap is declared with a particular typedef the interface variable would need this typedef to declare and assign a local copy.

How would I give the interface visibility to the VHDL typedef?

Answer 9

chr_sue

Full Access

2825 posts

January 16, 2018 at 10:47 am

In reply to ce_2015:

Your error message might depend on oher cntent in your VHDL pckage. Only types cn be shared between VHDL and SV.

Answer 10

ce_2015

Full Access

39 posts

January 16, 2018 at 10:55 am

In reply to chr_sue:

Quote:

In reply to ce_2015:
Your error message might depend on oher cntent in your VHDL pckage. Only types cn be shared between VHDL and SV.

And that is possible, and unfortunately I can't do anything about the other content. Returning to the original problem and that is getting a hierarchical reference into the VHDL into the UVM Component (Scoreboard). At the very least I have been able to get everything to compile when I suppress the 7053 error (the one that doesn't allow hierarchical references from packages).

I would prefer a better solution though if possible to giving the Scoreboard access to the regmap...

Answer 11

dave_59

Forum Moderator

7785 posts

January 16, 2018 at 6:06 pm

In reply to ce_2015:
The ability to interact across VHDL/SV language boundaries are tool specific features. You should contact your tool vendor directly for support.

- Dave Rich

Languages & Standards

Methodologies

Techniques & Tools

Universal Verification Methodology (UVM)

Featured Courses

Additional Courses

Formal-Based Techniques

Analog/Mixed Signal

UVM Forum

SystemVerilog Forum

Coverage Forum

Additional Forums

Implementation Patterns

Specification Patterns

Pattern Resources

UVM Cookbook

Coding Guidelines & Deployment

Coverage Cookbook

Upcoming & Featured Events

On Demand Seminars

Recording Archive

Mentor Training Center

Mentor Learning Center

Blog & News

Verification Horizons Publication

About Us

Training

Solution