How to read and write Through JTAG protocol?

UVM
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1

Hi all,
I am working on soc verification level. For that we are writing and reading from the soc through the JTAG interface in test mode.

                       OR

How to read and write from dut through JTAG protocol ?

please help me for proceed further.

Thanks in advance

2

In reply to VK_18:

This is a very broad topic. JTAG is just another interface to your DUT, just like SPI or AHB is, but specific to boundary scan architecture. How those scan chains are implemented is very design specific. Usually the tools the insert these scan chains have tools and testbenches the come as part of their package.

3

In reply to VK_18:

Hi all,
I am working on soc verification level. For that we are writing and reading from the soc through the JTAG interface in test mode.
OR
How to read and write from dut through JTAG protocol ?
please help me for proceed further.
Thanks in advance

Accessing the internal functionality through the JTAG interface is determinded by the JTAG protocol. Behind the JTAG you might have any other bus. My recommendation is to verify your DUT without the JTAG interface which is on top of your design. In a second step you can then verify the JTAG interface itself.

4

Thanks Dave_59 & chr_sue.

Can u share any DUT code & document related to JTAG for better understanding the JTAG protocol.

Thanks & Regards
VK_18

5

In reply to VK_18:

Simply search the internet for JTAG spc or read here:

6

In reply to VK_18:

First are you sure that you need to create separate test-bench for JTAG test mode? Most of the time the scan chain insertion tools they automatically generate test vectors to verify JTAG connectivity.

If yes, than in our system JTAG usually has TAP block, which allows to communicate easily with it. So I would recommend at first get that TAP module and use it to work with JTAG.

7

Hi…Is this a two wire or 4-wire JTAG interface? My memory for the 2-wire JTAG interface is a digit fluffy as I haven’t actually worked with that since 2012. For the present I will accept that it’s a 4-wire JTAG interface. On the off chance that I review accurately the Synopsys ARC centers appropriately execute the JTAG convention and will naturally stack the IDCODE guidance into the INSTRUCTION register at whatever point you go through Test Logic Reset (TLR)

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