How to randomly choose register UVC for each register access?

UVM
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1

Hi,

When we integrated UVM register into project, we may have more than one register UVCs, e.g. APB and JTAG.

Usually we setup the uvm_reg_map by invoke : XXX.map.set_sequencer(apb.sqr, apb_adapater). We could choose either APB or JTAG here, but it seems to me not both unless we have two uvm_reg_maps inside one register model, I want to know if we have a way dynamically choose APB or JTAG for each register access in one simulation ?

2

In reply to caowangyang:

https://verificationacademy.com/forums/uvm/multiple-frontdoor-sequences-same-ral#reply-54339

3

In reply to dave_59:

Hi, Dave,

I see, many thanks.