How to pass a value from env to the top

I created a top as shown below.

========= top.sv =============
module top;

bit clk;
logic rst;
wire logic rstb;
wire pend_finish;



assign pend_finish = End_of_Simulation;

endmodule

and here is my_env code shown below.

======== my_env.svh ==========

class my_env extends uvm_env;

`uvm_component_utils(my_env)


reg End_of_Simulation;

function void start_of_simulation_phase(uvm_phase phase);
EndOfSimulation = 0;
endfunction : start_of_simulation_phase

function void end_of_simulation_phase(uvm_phase phase);
    force EndOfSimulation = 1; 
endfunction : end_of_simulation_phase

===============================

I have little idea how to pass the End_of_Simulation value from my_env to the top module ??

In reply to zz8318:

You can use the config_db to do this. But you have to be carefully. Retrieving a value in the toplevel module from the config _db needs to be synchronized with the set. The get in the initial will be started earlier as the set.
But the question is why do you want to do this? The simulation stops automatically in the UVM when all steps are executed.

In reply to chr_sue:

I need to do more extra dump stuff in the end of the simulation for the test…
anyway, let me take a try with your suggestion, thank you

In reply to zz8318:

Can you use a final block to dump the required information?

In reply to cgales:

I am sorry I am a fresher in UVM world. Could you please give me a guide how to use a final block ?? Thank you

In reply to zz8318:

A finish block is a SystemVerilog construct similar to an initial block. Refer to the SystemVerilog LRM for additional information.