here is the TB
I have declared enum in my transcation
test_trans.sv
class test_trans extends uvm_sequence_item;
typedef enum int {TEST0,TEST1,TEST2} testname_type_enum;
…
…
endclass
in driver class I instantiated this uvm_sequence_item
protected test_trans driver_tr;
I am using “testname_type_enum” in case statement to figure out what driver should do when based on {TEST1,TEST2,TEST3},
which I am providing from sequence
First point is that, we should not be passing anything from the driver to monitor.
Monitor should be independent and picking the required data from the interface to interpret the transaction and other details. I don’t think there is any predefined way to pass anything from driver to monitor because ideally there shouldn’t be any connection between the 2. In case there was a way to connect the 2, everyone would find it is easier to pass data directly rather than picking it up and analyzing. (which would spoil the intent of verification itself)
One way you can pass would be to have a global variable which would take value in the driver and then accessed in the monitor. But it is better you don’t connect the 2.
P.S. : In the snippet you have provided, the following highlighted code might not work.
`uvm_do_with(req, {req.testname_type_enum == test_trans::TEST1;})
It’s a enum and not a variable of type enum. Might be a typo mistake, but just pointing out.