How to pass design path from command line and use it as hierarchy of design path

UVM
1

I want to pass design path from command line and want to use as hierarcy into my code.

Problem Statement,
From command line I will pass as “+PATH=TB_TOP.CHIP.BLOCK_A.BLOCK_B.CLK”
Now I would like to get this path using $value$plusargs function into my TB file.

For example,
string clk_sign;
void’($value$plusargs(“PATH = %s”,clk_sign));
@posedge(clk_sign);
$display($time);

As we are getting full path as string into clk_sign variable. I can not use directly as hierarcy path.

Is there any way we overcome this and convert this path from string format to actual design path.
OR
Any other suggestion to handle this scenario.

I am using VCS tool.

Thanks,
Pratik

2

In reply to pv@1234:

You cannot access signal names using a string within the SystemVerilog language. Your options are using the VPI C-language simulator interface or using tool specific commands, which are off-topic for this forum.

Another option is getting the path name as a +define at compile time, so there is no need to deal with strings.