How to mask the write data and read data in a register in UVM sequence

UVM
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1

Hi,

I want to mask the write and read data for a register in a sequence
Example :
I have a control register (ctrl_reg) with width of 32- bits
The control register has 2 fields status[11:0]- R/W(read/write) and reserved [31:12]-RO(read only)
while I am writing data the data is writing into 32-bits but while reading only the Read write is getting and my self checking is failing.
can anyone please help me how to mask the register so that it can write to only R/W fields and read from that fields
Please help me how to mask the register.

Thanks in advance,
Harshavardhan

2

In reply to Harsha vardhan:

This is a bug that was fixed in UVM 1800.2.

If you are using UVM 1.2 or earlier, you can set the field’s volatile bit when configuring the field as a workaround.