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  • how to make addresses randomised in write sequence and read sequence are same

how to make addresses randomised in write sequence and read sequence are same

UVM 6660
#sequence 39 #systemverilog 100
Sv-hustler
Sv-hustler
Full Access
38 posts
September 30, 2019 at 4:29 am

I have a write sequence and read sequence and i'm randomising write seq 10 times,so I will be generating 10 unique addresses.I want to randomise in read sequence with same 10 addresses that were generated in write sequence.

I think of using seed value or using a queue in write sequence and in read seq ill add constraint within!

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dave_59
dave_59
Forum Moderator
10658 posts
September 30, 2019 at 9:08 am

In reply to Sv-hustler:

See https://verificationacademy.com/forums/uvm/generating-unique-addresses-write-sequence#reply-45842

— Dave Rich, Verification Architect, Siemens EDA

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