I am new to RAL and recently I run into a case in which one register requires multiple mirror values to be maintained. I am hoping anyone could help me on this topic.
For demonstration, let's assume DUT has 2 registers exposed to user as below
Register PTR, address 0x0
Register A, address 0x4
Inside DUT, register A gets mapped to 2 different registers: A0 & A1. User is required to set proper value of PTR before access A: if PTR == 0, access to A gets redirected to A1, else redirected to A2. User can only observe access to address 0x4 ( address of register A ) in bus, all redirection happens inside DUT.
Example of access sequences:
A.write(val_0) // val_0 gets written to register A0
A.write(val_1) // val_1 gets written to register A1
A.write(val_2) // val_2 gets written to register A1
A.read( return_val) // return_value is val_0, not val_1 nor val_2
As shown, register A shall have 2 mirror values maintained, and any access to register A shall refer to PTR value to determine which mirror value shall be updated. I am not clear of how to do it. Does anyone have a potential solution? Thanks a lot !