Firstly, to understanding .update() functionality, I add the .mirror() method as the below.
then I add regmodel.update(status, UVM_BACKDOOR, .parent(this)); to update for fixing MISMATCHED between DUT and Mirrored value.
...
regmodel.reg_mem_addr.write(status, 32'h1234_DEF0);
regmodel.mirror(status,UVM_CHECK , .parent(this)); <<--- I added
//regmodel.update(status, UVM_BACKDOOR, .parent(this));//Error (no BackDoor path)
regmodel.update(status, UVM_FRONTDOOR, .parent(this)); <<-- I added
regmodel.mirror(status,UVM_CHECK , .parent(this));
//Read from the registers
regmodel.reg_intr.read(status, rdata);
Here’s my questions,
How does compiler know there is frontdoor path/backdoor path in uvm reg model?
After .write(), I expect the mirrored value, the desired value and the DUT register value are all to be the same value.
But when I check them by .mirror(), I got the error message “Register “regmodel.reg_ctrl” value read from DUT (0x0000000012341234) does not match mirrored value (0x0000000000000000)” I think mirrored value not updated by .write(). Even.update() not work. What am I missing the point?
The register model contains the information how the backdoor can access the registers by using add_hdl_path_slice and add_hdl_path.
These 2 configuration methods are specifying the path to the single regs.
In your code example you do not read from the design registers because you did not sett the path correctly.
In reply to UVM_LOVE:
The register model contains the information how the backdoor can access the registers by using add_hdl_path_slice and add_hdl_path.
These 2 configuration methods are specifying the path to the single regs.
In your code example you do not read from the design registers because you did not sett the path correctly.
Ah… It too hard to get a Normal register test tutorial. I got from verification.com.
I think this example is something wrong and too hard to understand accessibility for uvm reg model.
Anyway this example use .write() and .read() methods for example. and eventually these methods are working at the point of result view.
So I add in the middle of test sequence “.update()” or “.mirror()”…
AS your answer, This example onlt for test .write() and .read(). am I understand correctly?
If I don’t use BACKDOOR access, Do I need “add_hdl_path_slice” and “add_hdl_path”?
If yes, I modify my example only FRONTDOOR, U RAL - EDA Playground
But still it has mismatched between mirrored values and dut values after .write()
In your dma_adapter you specify in the funtion reg2bus only the WRITE direction. You do not specify what should happen in case of READ, i.e. returns the initial values of the data type.
In reply to UVM_LOVE:
In your dma_adapter you specify in the funtion reg2bus only the WRITE direction. You do not specify what should happen in case of READ, i.e. returns the initial values of the data type.
Yes I found what the wrong code. I fixed it. think it is working well.
I believe you do not understand the intent of the functions bus2reg and reg2bus.
reg2bus describes the direction from the register package to the DUT and bus2reg the way from the DUT to the registers in the UVM environment. In simple words reg2bus means WRITE and bus2reg READ.
In reply to UVM_LOVE:
I believe you do not understand the intent of the functions bus2reg and reg2bus.
reg2bus describes the direction from the register package to the DUT and bus2reg the way from the DUT to the registers in the UVM environment. In simple words reg2bus means WRITE and bus2reg READ.
Sir, Could you give me a clue for my problem? I think the adapter direction correctly implemented. I can’t find the problem.
Does kind property has one way diection?