How to improve as a verification engineer?

Hi. I have two years of experience in SystemVerilog and UVM.

In these two years, I mainly did tasks like:

  • Checking failing tests and fixing the verification environment accordingly or finding bugs inside RTL
    code.
  • Code add-ons to the chip’s verification environment like checkers, drivers and new tests.
  • Build verification environments for different modules from zero.
  • Adding UVM components like a driver and monitor to an existing verification environment.

Unfortunately, I think my knowledge and experience are not good enough in relation to the time I have been in the field. Therefore, I want to make a leap through homework, courses and change my workplace to a more challenging place.
My questions are:

  1. How to become a more professional verification engineer by practicing at home? (For example, recommendations on courses for experienced verification engineers that can suit me, recommendations on blocks for which verification environments can be made).
  2. How to prepare for a job interview with 2+ years of experience? (They usually ask questions like: how would you check a certain block - do you know any files with questions like this?)

Thanks, Dvir