How to implement UVM testbench for Asynchronous FIFO

UVM
1

I have done UVM based testbench for synchronous FIFO. Now I have to do it for an Asynchronous FIFO. How to implement the interface?( Both read and write clocks ) and how can i drive the seq. in driver.

Atleast please mention how should i proceed. ( Just main points)
Thanks in advance

2

In reply to Pavi:

I think it would be better if you proceed with two agents.

one agent is for write another agent is for read.

in write driver you can have write clk,with respect to it you can drive write data on the interface,in read driver you can have read clk,with respect to it you can drive read data on interface.

3

In reply to Pavi:

The only solution is to have 2 agents, one for Read another one for write, because it is specific to the asynchrounous fifo to have Independent Read and write cycles.

4

In reply to chr_sue:

Hi,

If we connect 2 sequencer (1 for read and 1 for write) and connect them to driver using 2 different TLM ports then I think only one agent is required.

5

In reply to piyushpatel123:

You need only 1 sequencer with 1 TLM port. In this case you have to have your access type (RD/WR as a data member in your sequence item. You can randomize this seq_itemto generate random access or using inline constzraints to constrain RD or WR.

6

In reply to chr_sue:

But since read and write are asynchronous we need two concurrent thread (1 for read and 1 for write) am I correct ?

7

In reply to piyushpatel123:

If you have only 1 driver, it does not make sense to have 2 sequencers. Let a RD-sequence and a WR-sequence run in a fork/join on 1 sequencer.

8

In reply to chr_sue:

So in that case I think read and write will become dependent on each other but we have to implement independent read and write in async fifo. Is my understanding correct ?

9

In reply to piyushpatel123:

If you have only 1 driver you need also an algorithm for selecting RD and WR. This makes the access also deterministic.

10

In reply to chr_sue:

So can we RD and WR concurrently in that case?

11

In reply to piyushpatel123:

I do not know what you mean with concurrently. If you have 1 driver with 1 virtual interface you can serve only 1 operation at a time. But the RD and WR sequence is running concurrently.

12

You shall also refer this thread!

https://verificationacademy.com/forums/uvm/verification-asynchronous-fifo

13

In reply to chr_sue:

Hi,
If you have one driver but 2 virtual interfaces then Is it ok to have only one agent ?
As you have mentioned earlier let RD-sequence and a WR-sequence run in a fork/join on 1 sequencer . But here if I use 2 virtual interfaces then both read and write operations can be done simultaneously . Right ?