I am new to verification, so I had a few basic questions.
I tried implementing APB slave model in UVM testbench, with DUT as APB protocol (with FSM states - idle, setup, enable and logic) and testing for read/write transaction in testbench.
Proceeding to complete verification of APB master-slave model, How to implement the master component and interaction between the master and slave components in the testbench?
Thank you