How to implement bus reset to UVM_RAL using predictor

UVM
1

I am using RAL to implement a certain set of registers and have implemented a register adapter to define bus2reg and reg2bus functions. The RAL registers are updated based on APB monitor through predictor.

However, I just realized that bus2reg function doesn’t have any support to set the reset value to RAL whenever APB reset is sampled. My APB monitor will capture both valid transactions as well as reset transactions to the analysis port and the same is received by the predictor model.

May I know how to make sure that the predictor will set the reset value of corresponding RAL registers whenever APB monitor sends a reset transaction?

Thanks
Abdus

2

In reply to abdus_k:

The reset value of each register has to be specified in the RAL register model. When asseerting the reset this value will be set in the registers itself. You do not need to send this value from the testbench.

3

In reply to chr_sue:

Hi chr_sue,

How would the RAL model understand bus reset assertion if we don’t define reset condition in bus2reg function in the adapter?

As far as I know, we need to define the function, bus2reg, to convert bus interface transaction into RAL compatible transaction but this function doesn’t have an option for defining bus reset. We only specify read and write transaction definitions based on the bus interface.

Cheers
Abdus