How to Handle Asynchronous reset in UVM Testbench

UVM
1

Hi,

Please suggest how to handle reset in UVM TB.
DUT has external RESET pin, which can be asserted, de-asserted multiple times in a test.
How to reset the UVC and ongoing sequences incase of reset and bring TB to reset state and then
start again.

Also, if you can provide link to relevant example, it will be of great help.

BR