How to get the string of current run test name in the default sequence?

UVM
1

I have a test with name “test_current_run”.
In test_current_run, the sequence “test_current_run_seq” is defined as default sequence.

In this “test_current_run_seq” sequence, is it possible to get the name of current test “test_current_run” as a string?

Thanks,

2

In reply to y-yang:

There are 2 methods available:

  1. virtual function string get_full_name(): returns the fullname including the hierachical path
  2. virtual function string get_name(): Returns the name of the object, as provided by the name argument
3

In reply to y-yang:

Assuming you have only one top level component instantiated by run_test, you can use

{uvm_root::get().top_levels[0],"_seq"}

to build the name of your sequence.

4

I am not really sure why you want to do this. Is the behavior of the sequence going
to change depending on which test (i.e test_name) it is invoked from? If so, it may
not be a good idea. I would rather create different sequences which can be invoked
from different tests.

Anyways if you still need it, one easy way is to use the config_db to store
the test_name during the build_phase of the test, and during the body of the sequence
you can extract the name from the config_db.

5

In reply to y-yang:

Thanks all. Problem solved.

6

In reply to logie:

I am not really sure why you want to do this. Is the behavior of the sequence going
to change depending on which test (i.e test_name) it is invoked from? If so, it may
not be a good idea. I would rather create different sequences which can be invoked
from different tests.
Anyways if you still need it, one easy way is to use the config_db to store
the test_name during the build_phase of the test, and during the body of the sequence
you can extract the name from the config_db.

could you please explain the drawback of changing behavior of sequence depending on test?

7

In reply to y-yang:
My 2cents.
You can of course use the command line processor of UVM to extract not only the testcase name called but seed and other parameters.

Just see some examples here

or
https://www.chipverify.com/blog/how-to-pass-a-command-line-argument-to-uvm-testbench

All methods
https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/base/uvm_cmdline_processor-svh.html

https://verificationacademy.com/cookbook/uvm/commandlineprocessor

Lastly, you can use plain systemverilog
$test$plusargs (user_string)
$value$plusargs (user_string, variable)