interface my_intf(logic clk);
parameter NUM_IO=32;
logic [NUM_IO-1:0] my_sig1;
endinterface
class my_driver extends uvm_driver;
virtual my_intf vif;
`uvm_component_utils(my_driver);
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual my_intf)::get(this, “”, “vif”, vif))
`uvm_fatal(“NO_VIF”,{“virtual interface must be set for: “,get_full_name(),”.vif”});
endfunction: build_phase
task run_phase(uvm_phase phase);
…
endtask
endclass
module my_top();
…
my_intf #(.NUM_IO(16)) intf(.clk(top_clk));
initial begin
uvm_config_db#(my_intf #(.NUM_IO(16))::set(null, “*”, “vif”, intf);
end
…
endmodule
I’m hitting uvm_fatal in my_driver and I think it’s because of the parameter value being 32 in the interface and when I set it to 16 in module my_top. It’s being interpreted as 2 different interfaces. Not sure how to fix this.
Help appreciated.
Thanks in advance.