How to get enum class based variable in module based assertion file

UVM
1

i want to get class based enum varible in module chckers file.

for example:

package eda_e1;
//`include "uvm_macros.svh"

typedef enum {A,B,C}adr_e; 


class example;
  
  rand adr_e adr;
  rand bit talk;
  
endclass
endpackage




import uvm_pkg::*;
`include "uvm_macros.svh"
//import eda_e1::*;
module tb;
 
  import eda_e1::*;
  example ex1;
  bit clk;
  
  bit s1,s2;
  s1=1'b1;
  #20
  s2=1'b1;
 // import uvm_pkg::*;
  property p1();
    @(posedge clk)  disbale iff(ex1.adr==A)
     s1 |-> ##4 s2;
    
  endproperty
  
 C1: assert property (p1);
  
   
   initial begin
     clk=1'b0;
     #5 clk=~clk;
   end
  initial begin
     ex1=new();
    
  end
  
  
  
endmodule

getting the error

vlog -writetoplevels questa.tops -timescale 1ns/1ns “+incdir+/playground_lib/uvm-1.2/src” -L /usr/share/questa/questasim//uvm-1.2 design.sv testbench.sv
** Note: (vlog-2286) testbench.sv(3): Using implicit +incdir+/usr/share/questa/questasim/uvm-1.2/…/verilog_src/uvm-1.2/src from import uvm_pkg
** Error: testbench.sv(7): (vlog-13006) Could not find the package (eda_e1). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
End time: 08:00:43 on May 11,2020, Elapsed time: 0:00:00
Errors: 1, Warnings: 0
Exit code expected: 0, received: 1

2

In reply to ramDV:

I believ you are pasting the wrong code, because the code below runs in my environment and I do not see problems with the enumeration type:

package eda_e1;
//`include "uvm_macros.svh"

typedef enum {A,B,C}adr_e;

class example;

rand adr_e adr;
rand bit talk;

endclass
endpackage

import uvm_pkg::*;
`include "uvm_macros.svh"
//import eda_e1::*;
module tb;

import eda_e1::*;
  example ex1;
  bit clk;
  bit s1,s2;

/*
property p1();
@(posedge clk) disbale iff(ex1.adr==A)
  s1 |-> ##4 s2;
endproperty

C1: assert property (p1);
*/
initial begin
  s1=1'b1;
  #20;
  s2=1'b1;
end
initial begin
  clk=1'b0;
  #5 clk=~clk;
end
initial begin
  ex1=new();
end
endmodule
3

In reply to chr_sue:

hi chr_sue,

My requirement is im writing a assertions in module but the enum variable is in transaction class need to get this enum variable in module…

why i need to get means i writing assertion for checking vip so the addrss mode is10bit and 7bit and speed modes also there in tranasction based oon this speed modes and address modes the assertion should work

4

In reply to chr_sue:

In reply to ramDV:
I believ you are pasting the wrong code, because the code below runs in my environment and I do not see problems with the enumeration type:

package eda_e1;
//`include "uvm_macros.svh"
typedef enum {A,B,C}adr_e;
class example;
rand adr_e adr;
rand bit talk;
endclass
endpackage
import uvm_pkg::*;
`include "uvm_macros.svh"
//import eda_e1::*;
module tb;
import eda_e1::*;
example ex1;
bit clk;
bit s1,s2;
/////////////This is my requeremnt to get the class enum varibale in the module/////////////
/*
property p1();
@(posedge clk) disbale iff(ex1.adr==A)
s1 |-> ##4 s2;
endproperty
C1: assert property (p1);
*/
initial begin
s1=1'b1;
#20;
s2=1'b1;
end
initial begin
clk=1'b0;
#5 clk=~clk;
end
initial begin
ex1=new();
end
endmodule

i need write assertion for the particular bit is high in transaction random packet based on this my assertion should work

5

In reply to ramDV:
You need to create a static variable copy of ex1.adr. SystemVerilog does not allow dynamic class variables in assertions because you get null references at time 0.

adr_e adr;
property p1();
@(posedge clk) disable iff(adr==A)
  s1 |-> ##4 s2;
endproperty
 
C1: assert property (p1);
  
initial begin
  s1=1'b1;
  #20;
  s2=1'b1;
  #100 $finish;
end
initial begin
  clk=1'b0;
  forever #5 clk=~clk;
end
initial begin
  ex1=new();
  forever @ex1.adr adr = ex1.adr;
end