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How to generate a generic verification environment for a DUT whose output wires changes according to the configuration?

rishabh
rishabh
Full Access
4 posts

Hi,
I have made a VIP for a DUT in UVM, but the problem i am facing is that there is wires in the interface( or DUT output wire) which changes according to the config parameter.

For eg For K =1 logic [SIZE_FOR_K1-1 :0]]mem_out_1; ....only 1 wire

For K=2 :2 wires
logic [SIZE_FOR_K1-1 :0]]mem_out_1; ......2 wires of different width
logic [SIZE_FOR_K2-1 :0]mem_out_1;
and so on...

DUT files are generated using scripts according to the configuration.

Now How can I alter my verification environment, so that i dont have to generate different files of my environment for different configuration.

PLease reply as soon as possible

Thanks in advance.

 

 

 

Answers

ktmills
ktmills
Full Access
4 posts

This is how I might do it.

package param_test_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
class default_test extends uvm_test;
`uvm_component_utils(default_test)

function new (string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass

class param_test #(int SIZE_FOR_K=0) extends default_test;
`uvm_component_param_utils(param_test#(SIZE_FOR_K))

function new (string name, uvm_component parent);
super.new(name,parent);
$display("here\n");
endfunction
endclass

endpackage

module dut();
parameter SIZE_FOR_K=1;
wire [SIZE_FOR_K-1:0] dut_wire;

endmodule

module test();
localparam int SIZE_FOR_K=1;
import uvm_pkg::*;
import param_test_pkg::*;

dut #(SIZE_FOR_K) my_dut();

initial
begin
default_test::type_id::set_type_override(param_test#(SIZE_FOR_K)::get_type());
run_test("default_test");
end

endmodule

3

COMMENTS

HIDE ▲

thanks for the reply.....but the problem is that wire width alone doesn't change ...no of wires also changes according to the configuration... For e.g
if k=1 i have one wire of size =10 bits
if k=2 i have 2 wires
if k=3 i have 3 wires
and so on..

and these are output wires ...so my monitor logic changes according to the no of wires of the DUT.

so wat can i do for this problem, whether to generate the code of monitor through the scripts or something else ...

Please reply soon
thanks in advance

[code]
interface dut_interface #(SIZE_FOR_K=1) ();
import uvm_pkg::*;
wire [SIZE_FOR_K-1:0] [7:0] A;
genvar i;
generate
for(i=0; i

thanks a lot ..but 1 thing if u have taken fixed size of wires of 8 bit ...but if i want to make it also configurable of different width how can i do it ???