Hi all,
With regards to the UVM Environment, I have two file;
testcase.svh and sequence.svh
In sequence.svh, I have one declaration and task;
///////////////////////////////////////
typedef byte_t data_payload;
USB_OUT_TASK (
input a,
input byte_t data_payload[],
etc....
);
/////////////////////////////////////
In testcase.svh, I need to use this data_payload to enter number of elements;
////////////////////////////////////////
bit [7:0] data_payload;
task body();
USB_OUT_TASK (
.a(a),
.data_payload(data_payload),
etc…)
endtask
///////////////////////////////////////////
Where data_payload is the variable that defines the number of elements that I need to write to the testcase. By default, if we run the testcase, number of elements written will be zero.
case1: bit [7:0] data_payload = {'h01, 'h02, 'h03};
OUTPUT: 3 elements
case2: bit [7:0] data_payload [0:3] = {'h01, 'h02, 'h03, 'h04};
OUTPUT: It shows 4 elements what we have written
Now, if I want to write 500 elements, I should write;
bit [7:0] data_payload = {'h01, 'h02, 'h03, 'h04, … till 500 elements…};
and the testcase becomes too lengthy, everytime I need to enter manually.
Can anyone suggest how to include a mechanism so that If I just mention as 100 to any variable, it should write 100 elements. Because I need to verify the scenario for 1000, 5000 etc…
I have tried parameter method, declaring for loops, using $urandom_range etc… but I couldn’t get control over this. Kindly show me the example for this.