Dear All,
I'm trying to understand uvm phase process. Especially, we can implement forever statment such as the below example.
https://www.chipverify.com/uvm/uvm-monitor
class my_monitor extends uvm_monitor;
`uvm_component_utils (my_monitor)
...
function new (string name, uvm_component parent)
super.new (name, parent);
endfunction
virtual function void build_phase (uvm_phase phase)
super.build_phase (phase);
endfunction
virtual task run_phase (uvm_phase phase);
forever begin
...
data_obj.data = vif.data;
data_obj.addr = vif.addr;
...
if (enable_coverage)
data_obj.cg_trans.sample();
// Send data object through the analysis
mon_analysis_port.write (data_obj);
end
endtask
...
endclass
As you can see the above, there is implemented with foreever statement.
I'm wonder that if we use forever statment, who/how does kill it?
In https://verificationguide.com/uvm/uvm-monitor/ , some article answered by "don't use forever statments".
Even if I implement a raise/drop objection in run_phase, doesn't forever stop?
