How to drive/force a internal design signals

UVM
,
1

Hi,

I am doing fault testing and i want to force/drive some of the Design signals from the testbench. How can i do that ?
What i did so far :




interface intf ();

bit amux;

always @ (*) begin
if (amux)
force top.d.ecc = 32'h11111111;

else 
force top.d.ecc = 32'h00000000;
end

endinterface


class mysequence extends uvm_sequence // This is basically driver class 

virtual intf vif;

task mytask ();
vif.amux =1;
endtask

endclass

Please let me know if this is correct way.

Thanks,
Tejas

2

In reply to tejasakulu:

You are doing the force in the wrong place. The sequence should never know the signals of your DUT. You can implement the force in the driver or from the toplevel module of your UVM test bench.