How to drive signals with two clocks in driver?

UVM
1

I am trying to drive signals with 2 different clocks. Can anyone suggest how to use two clocks in driver?

2

In reply to v_govardhan:

Same way as single clock case
Make 2 clock inputs for your interface than get that interface in the driver and use that clocks. Generate the input 2 clocks in the top tb and pass them to interface, than put the interface in config_db

3

In reply to haykp:

I don’t belive it is so easy.
It depends on your intreface protocol. How it is working?
Do you have an input clock synchronizing the data to the DUT and an output clock synchronizing the data coming from the DUT or how doeas it work.

4

I need to perform write with one clock and read with other clock.
I used 2 clocks in the driver but each data is driven two times.

5

In reply to v_govardhan:

Could you please show your driver code?
I do not unerstand what you are saying in your last post.

6

In reply to v_govardhan:

So your driver need to check if the operation type is read than use read_clock,
if operation type is write than use write clock.
You can have one case there which checks the operation type from received sequence_item, and depending on operation type calls either Write or Read task.
Each task has its own clock.

7

In reply to haykp:

May be you need something like this in driver. but you have to show code for us to tell.


case (tr.apb_cmd)
         apb_rw::READ:
           begin
             @ (posedge vif.uclk);
           drive_read(tr.addr, tr.prdata);  
         end
         apb_rw::WRITE:
           begin 
             @(posedge vif.pclk);
              drive_write(tr.addr, tr.pwdata); 
           end
       endcase
8

This is my driver code

@(vif.posedge write_clock)
vif.write_enable=trans.write_enable;

@(vif.posedge read_clock)
vif.read_enable=trans.read_enable;

9

In reply to v_govardhan:

This means you are writing on each write_clock and you are reading on each read_clock.
I believe this is not what you want to do.