How to drive the packet to dut

Could any one please help me in writing the verification code for yapp packet router.I don’t have any experience in verification field.i’m a fresher.
I am creating yapp uvc.
I have a packet class when i am driving the packet to dut its not getting any value from driver.iam unable to find my mistake could any one please help me.
this is my packet class : i declared short_yapp_packet class as my packet class in test class.

typedef enum{BAD_PARITY,GOOD_PARITY}parity_t;
class yapp_packet extends uvm_sequence_item;

            rand bit [5:0]length;
            rand bit [1:0]addr;
            rand bit [7:0]payload[];
                 bit [7:0]parity;
rand int packet_delay;
rand parity_t parity_type;

`uvm_object_utils_begin(yapp_packet)
  `uvm_field_int(length,UVM_DEFAULT)
  `uvm_field_int(addr,UVM_DEFAULT)
  `uvm_field_array_int(payload,UVM_DEFAULT)
  `uvm_field_int(parity,UVM_DEFAULT)
  `uvm_field_int(packet_delay,UVM_DEFAULT)
  `uvm_field_enum(parity_t,parity_type,UVM_DEFAULT)
`uvm_object_utils_end

//constructor

function bit[7:0]calc_parity();
calc_parity={length,addr};
for(int i=0;i<length;i++)
begin 
calc_parity =calc_parity^payload.xor();
end 
endfunction 

function void post_randomize();
if(parity_type==GOOD_PARITY)
parity=calc_parity();
else 
parity=~parity;
endfunction 

constraint valid_address{addr>=0;addr<3;} 
constraint packet_length{length>0;length<64;}
constraint pck_size{length==payload.size();}
constraint pck_delay{packet_delay>0;packet_delay<=20;}
   
endclass

class short_yapp_packet extends yapp_packet;

`uvm_object_utils(short_yapp_packet)

//constructor 
constraint packet_length{length<15;}
constraint valid_address{addr>=0; addr<2;}
endclass

sequence: in sequence class i am driving 3 packets to 3 different addresses (i was taken default sequence is yapp_012_seq in test class)

class yapp_sequence extends uvm_sequence#(yapp_packet);
`uvm_object_utils(yapp_sequence)

//constructor

virtual task body();
`uvm_info(get_type_name(),"starting of randomization",UVM_HIGH);
repeat(5)
begin
`uvm_do(req)
end 
endtask 
endclass

class yapp_012_seq extends yapp_sequence;
`uvm_object_utils(yapp_012_seq)

//constructor
virtual task body();
`uvm_info(get_type_name(),"starting of randomization to send 3 packets to 3 address locations",UVM_HIGH)

`uvm_do_with(req, {addr == 0;})
`uvm_do_with(req, {addr == 1;})
`uvm_do_with(req, {addr == 2;})
endtask
endclass 

driver :

class yapp_driver extends uvm_driver#(yapp_packet);
//virtual interface declaration
//yapp_packet handle
	 
`uvm_component_utils_begin(yapp_driver)
 `uvm_field_object(req, UVM_ALL_ON)
 `uvm_component_utils_end

//new() constructor

//build_phase
virtual function void build_phase(uvm_phase phase);
  if(!yapp_vif_config::get(this,"","vif",vif))
    `uvm_fatal("NOVIF",{"No virtual interface set for:",get_full_name(),".vif"})
super.build_phase(phase);
endfunction

//reset_phase 
virtual task reset_phase(uvm_phase phase); 
 begin 
   @(posedge vif.rst);
     `uvm_info(get_type_name(),"Reset OBSERVED",UVM_MEDIUM)
	  vif.in_data<=8'hz;
	  vif.in_data_vld<='z;
	 end 
endtask  
virtual task send_to_dut(yapp_packet packet);
 fork    forever 
  begin 
      vif.drv.in_data_vld <=1'b1;
   @(negedge vif.clk iff((!vif.drv.in_suspend)&&(vif.drv.in_data_vld)));
    begin 
      `uvm_info(get_type_name(),$sformatf("sending the packet  length :%d \t addr :%d \t payload : %h ",packet.length,packet.addr,packet.payload),UVM_MEDIUM)
        vif.drv.in_data<={packet.length,packet.addr};
		for(int i=0;i<packet.length;i++)
		begin 
		vif.drv.in_data<=packet.payload[i];
		end 
	end 
		vif.in_data_vld <=1'b0;
		@(negedge vif.clk iff((!vif.drv.in_suspend)&&(!vif.drv.in_data_vld)));
		 begin 
		 `uvm_info(get_type_name(),$sformatf("sending the packet  parity :%d",packet.parity),UVM_MEDIUM)
		  vif.drv.in_data <=packet.parity;
	     end  
	@(vif.drv)
	repeat(packet.packet_delay);
	repeat(2)@(vif.drv);
  end 
join 	
endtask    	
virtual task main_phase(uvm_phase phase); 
forever 
 begin 
 @(vif.drv);
seq_item_port.get_next_item(req); 
 send_to_dut(req);  
seq_item_port.item_done(); 
end 
endtask  

virtual function void start_of_simulation_phase(uvm_phase phase);
`uvm_info(get_type_name(),"driver start_of_simulation_phase",UVM_HIGH)
endfunction
endclass

Dharani,

As you are new to the verification, I would suggest you to improve on your debugging skills.
Try to isolate the problem, currently you have too many components to be looked at. Few points to be looked at:

  • are you able to drive data using base sequence and base packet class. If yes then driver is working fine otherwise there can be issue with driver also.
  • in your extended packet class you have rewritten constraint for packet_length which can solve with length set to 0, making your packet with empty payload.
  • print packet in sequence before sending to driver to ensure packet formation is correct.

Thanks,
Rohit

In reply to rohitk:

Thank you…