How does the register model work in the below scenario?

Example I have a APB access adapter for register modelling so that when i do a write/ read on the register in DUT the same will be reflected in Register model also. What if i do the same through Backdoor access. As in Back door access i am simply putting the register hierarchy in the rtl to do write/read.

In reply to Arun_Rajha:

Example I have a APB access adapter for register modelling so that when i do a write/ read on the register in DUT the same will be reflected in Register model also. What if i do the same through Backdoor access. As in Back door access i am simply putting the register hierarchy in the rtl to do write/read.

same value will be reflected in register model for back door access also.

different between front-door and back-door is:

  1. front-door : transaction happen through protocol interface and it is time consuming.
  2. back-door : transaction happen in 0 simulation time by directly modifying/reading the register.

In reply to Rahulkumar Patel:

One thing to add. If you are doining a read/write through backdoor r a peek/poke then both register models will be updated, the RTL registers and the mirror in the testbench.