How do you determine if a design should split up into blocks vs full chip?

When doing verification and creating sub-environments, how do you determine if the design should be split up? What are some characteristics a DV Engineer look for?

In reply to VerifEx:

I would look for standard interfaces between blocks (for example, APB, APB, etc.). This makes it easy to interface with these blocks by re-using existing UVCs.

I would also look for how well blocks are documented. If there isn’t much investment in documentation, what might be the case is that later in the project there may be a decision to change the blocks around (move stuff from one to the other), which will negatively impact your verification.

In reply to VerifEx:

Another aspect is the complexity of a sub-block. If yoiu have a highly complex sub-block with a huge amount of functionality it is useful to create a sub-environment.
Generally, there are no common rules, because it depends always on your specific situation.