How do I start monitor after delay for example 3us?

UVM
,
1

Hi all,

I have a test in which two sequences A and B are called on separate virtual interfaces to DUT. Inside scoreboard - a reference model produces correct output only after sequence A is done. I would like to start monitor only after sequence A is done. I know roughly how long it takes for sequence A to finish. sequence A is only called once during test. Can I set a bit in my monitor and control it from test? Any other suggestions?

Thanks

2

In reply to gupadhya:

Roughly is not accurate neough. Simply trigger an event when sequence A has been finished and start with the execution in the monitor.

3

In reply to chr_sue:

class adc_uvc_monitor extends uvm_monitor;
    `uvm_component_utils(adc_uvc_monitor)
     
    event                 rif_seq_done; 
    virtual adc_uvc_if  mladc_adc_if;
    adc_mon_item        mladc_mon_item;
    uvm_analysis_port #(adc_mon_item) item_collected_port_adc;
    
    function new(string name="adc_uvc_monitor", uvm_component parent);
        super.new(name,parent);
    endfunction : new
    
    function void build_phase(uvm_phase phase);
        super.build_phase(phase); 
        item_collected_port_adc = new("item_collected_port_adc", this);
    endfunction : build_phase
    
    function void connect_phase(uvm_phase phase);
        if (!uvm_config_db #(virtual adc_uvc_if)::get(null, "*", "adc_uvc_vif", this.mladc_adc_if)) begin
            `uvm_error("connect", "ADC virtual interface not found")
        end
        mladc_mon_item   = adc_mon_item::type_id::create("mladc_mon_item", this);
    endfunction : connect_phase
    
    virtual task run_phase(uvm_phase phase);
        forever begin
            @(posedge mladc_adc_if.rst_n);
            wait(rif_seq_done.triggered);
            `uvm_info(get_type_name(), $sformatf("About to start ADC monitor\n"), UVM_NONE);
            fork
                monitor();
            join_none
            @(negedge mladc_adc_if.rst_n);
            disable fork;
        end        
    endtask : run_phase
    task    monitor();
        forever begin
            @mladc_adc_if.cb2;
            mladc_mon_item.data_p = mladc_adc_if.cb2.data_p;
            mladc_mon_item.vin_n  = mladc_adc_if.cb2.VIN_N_S;
            mladc_mon_item.vin_p  = mladc_adc_if.cb2.VIN_P_S;
            item_collected_port_adc.write(mladc_mon_item);
        end      
    endtask
endclass

Inside sequence I am doing -
`uvm_info(get_type_name(), $sformatf(“Triggered rif_seq_done\n”), UVM_NONE);
->uvm_test_top.mtop_tb_env_h.adc_env_h.agent_h.adc_monitor_h.rif_seq_done;

Getting elab error -
xmelab: *E,CUVUNF (/prj/analog/ace_ip_tsmc22nm/sandiego/work_v100/gunjanu_mladc_2/design_project/verif_modules/verif/sim/tests/autoseq_tests/sequence_lib/src/mladc_rif_seq.sv,144|76): Hierarchical name component lookup failed at ‘uvm_test_top’.

So question is how do I trigger event inside monitor from a sequence?

4

In reply to gupadhya:

The error message is correct. The sequence does not know anything about your testbench topology.
I recommend to use the uvm_event instead of the simple SV event together with the uvm_event_pool. This solves the probelm with the topology.