I created a simple UVM platform. when I run the top_test, I got fatal errors. Could you please help me. It seems the connection between monitor and subscriber is the source of error.
================= UVM Test =================
class top_test extends uvm_test;
`uvm_component_utils(top_test)
myenv e;
my_sequence s;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
e=myenv::type_id::create("e",this);
endfunction
task run_phase(uvm_phase phase);
s=my_sequence::type_id::create("s",this);
phase.raise_objection(this);
s.start(e.ag.seqer);
phase.drop_objection(this);
endtask
endclass
================= UVM Environmnet =================
class myenv extends uvm_env;
`uvm_component_utils(myenv)
myagent ag;
mysubscriber sb;
function new (string name="myenv", uvm_component parent);
super.new(name,parent);
endfunction
function void uvm_build_phase (uvm_phase phase);
super.build_phase(phase);
ag=myagent::type_id::create("ag",this);
sb=mysubscriber::type_id::create("sb",this);
endfunction
function void connect_phase(uvm_phase phase);
ag.mon.aport.connect(sb.analysis_export);
endfunction
endclass
================= UVM Subscriber =================
class mysubscriber extends uvm_subscriber #(tr) ;
`uvm_component_utils (mysubscriber)
logic [7:0] golden [2**16-1:0];
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction
virtual function void write(tr t);
if (t.oper==read) assert (t.data==golden[t.addr]) `uvm_info("SB", $psprintf("correct read opearion addr=%h, data =%h, op=%s", t.addr, t.data, t.oper),UVM_HIGH);
if (t.oper!=nop) begin
golden[t.addr]= t.data;
`uvm_info("SB", $sformatf("write operation is performed in golden memory for the operation addr=%h, data =%h, op=%s", t.addr, t.data, t.oper),UVM_HIGH);
end
endfunction
endclass
================= UV Agent =================
class myagent extends uvm_agent;
`uvm_component_utils(myagent)
mymonitor mon;
mydriver drv;
mysequencer seqer;
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
mon=mymonitor::type_id::create("mon",this);
drv=mydriver::type_id::create("drv",this);
seqer=mysequencer::type_id::create("seqer",this);
endfunction
function void connect_phase(uvm_phase phase);
drv.seq_item_port.connect(seqer.seq_item_export);
endfunction
endclass
QuestaSim-64 vlog 10.6c Compiler 2017.07 Jul 26 2017
Start time: 01:47:50 on Aug 19,2019
vlog -reportprogress 300 -f compile.f
– Compiling module memory
– Compiling interface memory_if
– Compiling package globals
– Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) package.sv(5): Using implicit +incdir+C:/questasim64_10.6c/uvm-1.1d/…/verilog_src/uvm-1.1d/src from import uvm_pkg
– Compiling package top_sv_unit
– Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
– Importing package globals
– Compiling module top
Top level modules:
top
End time: 01:47:51 on Aug 19,2019, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
End time: 01:47:53 on Aug 19,2019, Elapsed time: 0:01:49
Errors: 2, Warnings: 1
vsim -voptargs=“”+acc"" top “+UVM_TESTNAME=top_test” “+UVM_NO_RELNOTES”
Start time: 01:47:53 on Aug 19,2019
** Note: (vsim-3813) Design is being optimized due to module recompilation…
Loading sv_std.std
Loading work.memory_if(fast)
Loading mtiUvm.uvm_pkg
Loading work.globals(fast)
Loading work.top_sv_unit(fast)
Loading work.top(fast)
Loading work.memory_if(fast)
Loading work.memory(fast)
Loading mtiUvm.questa_uvm_pkg(fast)
Loading C:/questasim64_10.6c/uvm-1.1d\win64\uvm_dpi.dll
----------------------------------------------------------------
UVM-1.1d
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
UVM_INFO @ 0: reporter [RNTST] Running test top_test…
** Fatal: (SIGSEGV) Bad handle or reference.
Time: 0 ns Iteration: 15 Process: /uvm_pkg::uvm_phase::m_run_phases/fork#1847_4f62b202 File: C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_common_phases.svh
Fatal error in Function globals/myenv::connect_phase at env.sv line 19
HDL call sequence:
Stopped at env.sv 19 Function globals/myenv::connect_phase
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_common_phases.svh 96 Function uvm_pkg/uvm_connect_phase::exec_func
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_bottomup_phase.svh 108 Function uvm_pkg/uvm_bottomup_phase::execute
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_bottomup_phase.svh 81 Function uvm_pkg/uvm_bottomup_phase::traverse
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_bottomup_phase.svh 61 Function uvm_pkg/uvm_bottomup_phase::traverse
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_bottomup_phase.svh 61 Function uvm_pkg/uvm_bottomup_phase::traverse
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_phase.svh 1156 Task uvm_pkg/uvm_phase::execute_phase
called from C:/questasim64_10.6c/win64/…/verilog_src/uvm-1.1d/src/base/uvm_phase.svh 1847 Task uvm_pkg/uvm_phase::m_run_phases