Dear All,
Now I'm trying to understand a UVM Register test method.
Once to know it, I make a simple register model and test class as the below.
// Code your testbench here
// or browse Examples
module test();
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "registers.sv"
class test extends uvm_test;
uart_ctrl_reg_model_c reg_model;
uvm_reg regs[$]; // Add
function void build();
uvm_reg::include_coverage("*", UVM_CVR_ALL);
reg_model=uart_ctrl_reg_model_c::type_id::create("reg_model", this);
reg_model.build();
endfunction
task run();
reg_model.reset();
foreach(regs[i]) begin // Add foreach to identify all registers name
`uvm_info(get_type_name(), $psprintf("TEST = %s" , regs[i].get_name ), UVM_LOW)
end
endtask
`uvm_component_utils(test)
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass
initial run_test("test");
endmoduleTo see the all register's name I added foreach keyword. But it doesn't work. nothing happened at all.
If I assuming is correct, there doesn't connect between uvm_reg regs[$] and register model class But not sure.
So my question is that how do I get my all registers into regs[$] ?
Here is implemented https://www.edaplayground.com/x/22pv
