How to disable RAL registers creation from env

UVM
,
1 
class register1  extends uvm_reg;

      `uvm_object_utils(register1  )

      rand uvm_reg_field field1;
      rand uvm_reg_field field2;
      rand uvm_reg_field field3;

      covergroup cg_field_values ();
          option.per_instance = 1;
          	cg_field1 : coverpoint field1.value ;
		cg_field2 : coverpoint field2.value ;
		cg_field3 : coverpoint field3.value ;
      endgroup

      // Constructor
      function new(string name = "eth_f_all_reg_config_urm");
         super.new(name,32,build_coverage(UVM_CVR_FIELD_VALS));
            if (has_coverage(UVM_CVR_FIELD_VALS)) begin  			
         cg_field_values = new();
         cg_field_values.set_inst_name({get_full_name(), ".cg_field_values"});
         end
      endfunction : new

       
      // Build
      virtual function void build();
      // creating and configuring reg fields
       endfunction

     function void sample_values();
         super.sample_values();
         if (get_coverage(UVM_CVR_FIELD_VALS)) begin
            if(cg_field_values!=null) cg_field_values.sample();
         end
      endfunction
endclass


class register2  extends uvm_reg;

      `uvm_object_utils(register2  )

      rand uvm_reg_field field1;
      rand uvm_reg_field field2;
      rand uvm_reg_field field3;

      covergroup cg_field_values ();
          option.per_instance = 1;
          	cg_field1 : coverpoint field1.value ;
		cg_field2 : coverpoint field2.value ;
		cg_field3 : coverpoint field3.value ;
     endgroup

      // Constructor
      function new(string name = "eth_f_all_reg_config_urm");
         super.new(name,32,build_coverage(UVM_CVR_FIELD_VALS));
            if (has_coverage(UVM_CVR_FIELD_VALS)) begin  			
         cg_field_values = new();
         cg_field_values.set_inst_name({get_full_name(), ".cg_field_values"});
         end
      
      endfunction : new
       
      // Build
      virtual function void build();
      // creating and configuring reg fields
       endfunction

    function void sample_values();
         super.sample_values();
         if (get_coverage(UVM_CVR_FIELD_VALS)) begin
            if(cg_field_values!=null) cg_field_values.sample();
         end
    endfunction
endclass

class my_reg_block  extends  uvm_reg_block;

       `uvm_object_utils(my_reg_block  )

      rand register1 reg1;
      rand register2  reg2;

 //Constructor
      function new(string name = "my_reg_block");
         super.new(name,build_coverage(UVM_CVR_ALL));
         endfunction : new

      //Build
      virtual function void build();
         
         // Creating and configuring registers
endfunction

endclass

class my_env extends uvm_env;

my_reg_block reg_b;

/// inside build_phase ()

      reg_b = my_reg_block::type_id::create("my_reg_block");
      reg_b.build();

endclass

I have shown the 2 template registers in my register blocks .I have many registers in my reg_block similar to them.
All those register files are getting generated using code generator.

They are passing UVM_CVR_FIELD_VALS when creating parent from new function of register1 and register2 …
They are getting created in my env.

I don’t want to create those registers. If i change UVM_CVR_FIELD_VALS to UVM_NO_COVERAGE , they are not getting created.
As i mentioned , they are getting generated from code generator. If i change register files, they will get overriden by the registers that are generated in next release .
I need to change them manually again.

I want to control register creation from my env. Is there any way to do that?

I tried adding below in my env build_phase after creating reg_block, but it did not work

reg_b.set_coverage(UVM_NO_COVERAGE);

Please suggest me a better way!

Thanks in advance.

2

In reply to sameermsa:

Your question isn’t clear.

You mention using “UVM_NO_COVERAGE” which seems that you want to not create any covergroups.

Is your intention to not create the register block? Not create certain registers? Not create coverage for all registers? Not create coverage for only certain registers?

3

In reply to cgales:

Hi,

I don’t want to create all registers in given register block.

Thanks,
Sameer Mohammad

4

In reply to sameermsa:

uvm_coverage_model_e is a builtin masking mechanism in the UVM for controlling construction of the coverage model, which can mirror the register model. There is no similar mechanism for controlling the construction of registers. The code generator that builds the register model would have to implement that for you, or you have have to manually modify the code to put such a mechanism in place yourself.

5

In reply to dave_59:

Thanks dave for clarifying this.