How to Disable or Override the previously done set_inst_override?

UVM
1

Hi,

I am using set_inst_override to override the base_sequence with actual_sequence which eventually runs on the master sequencer.

In the base_test I have this code to start the sequencer ::

master_base_seq seq = master_base_seq::type_id::create(“seq”,this,“masterName”);
seq.start(top.virtual_sequencer.masterSequencer);

Now, in test case I am using the set_inst_override to replace the master_base_seq instance ::

master_base_seq::type_id::set_inst_override(master_user1_seq::get_type,“masterName.seq”);

Above code works as intended and I see in the log that master_user1_seq is getting started on the master’s sequencer.

Now, later in the test I need to change the override such that I can start master_user2_seq.

But still the master_user1_seq gets started on the master’s sequencer.

When I print the uvm_factory after doing the second override ::
I see that both inst_override is shown as registered with factory and only the first one gets considered.

Instance Overrides:

Requested Type Override Path Override Type

------------------------- --------------------------------------------------- ---------------------------------

master_base_seq masterName.seq master_user1_seq

master_base_seq masterName.seq master_user2_seq

Here I cannot use set_type_override as it will override the type everywhere and I need to override the different sequences for different masters.

Is there a way to disable the previously set inst_override and set another inst_override?

I guess, the subsequent inst_override should override the previous one.

Please help, is there a workaround to achieve the behavior I am looking for?

Thanks,
Chintan

2

In reply to chintanmehta:

Did you try

master_user1_seq::type_id::set_inst_override(master_user2_seq::get_type,"masterName.seq");
3

In reply to dave_59:

Hi Dave,

Thanks for the suggestion. It works!

However, I feel that this is just unnecessary and just creates multiple layers of overrides which can become hard to debug later and also confusing to figure out which sequence to use next for override.

In the meantime,

I ended-up updating the uvm-1.2 library which can support the way I was trying to change the override.

I simply check for the incoming original_type and full_inst_path for the set_inst_override and if it matches with any existing override than update it with the ovr_type and ovr_type_name for the current call.

This way, I can use same original_type always to override with new type.

This makes the set_inst_override usage in-line with set_type_override usage.
Also, for a given original_type and full_inst_path factory has to hold single override at given time and this makes it easy to debug.

How can I propose this update to be incorporated in the upcoming uvm version?

Let me know your opinion on this.

Thanks,
Chintan

4

In reply to chintanmehta:

I strongly discourage modification of the UVM base class library yourself—it becomes a maintenance and migration headache later.

Instead I suggest using uvm_config_db#(uvm_object_wrapper)::set() which has the last-write-wins use model you are looking for.

One thing that does not make sense to me is you are calling create() in your base test, and overrides in your extended tests? Then how are you distinguishing between the different instance?

5

In reply to dave_59:

I agree about not to change uvm library and maintain locally.

However, my update makes the set_type_override and set_inst_override usage same.

Wanted to see if it can be included in next update.

Regarding the last question, in my base_test when I create the base_seq handle I know the masterName for which it being created and pass it as third argument and I can use the masterName later in the testCase for override call.