How to disable assertion in side uvm object from test

UVM
, ,
1

I am looking for way to disable assert in side uvm component for certain test. Bellow simple code represent my env, with comment for requirement. I thought i can use $assertoff. I can modify uvm component if required additional instrumentation to achieve this. Thanks,

import uvm_pkg::*;
`include "uvm_macros.svh"

class tb_env extends uvm_component;

   `uvm_component_utils(tb_env)

   int exp_val = 0;
   int act_val = 0;

   function new(string name = "tb_env", uvm_component parent = null);
      super.new(name, parent);
   endfunction

   virtual task run_phase (uvm_phase phase);
     super.run_phase(phase);
     phase.raise_objection(this);
     #10us;
     ASRT: assert ( exp_val == act_val) else
       `uvm_error(get_name(), "Error");
     #10us;
     `uvm_info(get_name(), "Done env", UVM_LOW);
     phase.drop_objection(this);
   endtask : run_phase

endclass

program tb_run;

initial
begin
   tb_env env = new("env");

   // Requirement: Disable assertion env.ASRT with system call $assertoff(...)

   fork
     run_test();
     begin
      #5us;
      env.exp_val = 1;
     end
   join
end
endprogram
2

In reply to albert.waissman@intel.com:

see 16.4.4 Disabling deferred assertions in the SV Standard.