How to create the queue array of class from text file

rupeshblr · December 1, 2020, 5:48pm

Hi,
Could anyone tell me how to create the queue of class from text file.
My text file contain address , wdata, rdata, rd_mask value , wr_mask value.

Text file (data.txt) :-
F0000000 FFFF 00FF 00FF
F0000004 AAAA 0000 00FF
…
…

typedef enum { WRITE,READ,R0,WO} reg_kind_t;

class packet_reg extends uvm_object;

bit [31:0] addr;
bit [31:0] wdata; //default data @reset
bit [31:0] rdata; //exp rdata
bit [3:0] wr_mask; //Compare data mask bits
reg_kind_t reg_kind; //register kind [RD/WR/RO/WO]

//predict expected rdata with mask
// constraint c_rdata { rdata = wdata & wr_mask; }

`uvm_object_utils(svci_reg)

function new(string name = “packet_reg”);
super.new(name);
endfunction

endclass : packet_reg

class reg_wr_rd_test extends uvm_test;
…
…
packet_reg wr_rd_reg_addr_array_q[$]; → queue of class

fd = $fopen (“data.txt” , “r”);

while (!$feof (fd)) begin 
  $fgets (line ,fd);
  $display ( "line = %s " , line);

< How to create the object and the load the data into queue >

endclass

chr_sue · December 1, 2020, 6:49pm

In reply to rupeshblr:

A few remarks first:
(1) Your text file has only 4 entries and not 5 as your packet has.
(2) You are defining a curious enumeration type. The first 2 entries are access types the last 2 are policies (RO, WO). I’d understand having RW as the first.
(3) Why do you need a class for your packet type? It could be simply a struct.

To split your read data into seperate data fields you can use the SV system function $fscanf.
See the details in chapter
21.3.4.3 Reading formatted data
of the IEEE of SV.

rupeshblr · December 2, 2020, 8:32am

In reply to chr_sue:

Hi,

I am trying to create the expected data for register wr_rd. I have standard file from where all the register information is preset (address, wr_mask, rd_mask) . i am driving the four value from BFM (ffff, AAAA, 5555, 0000). and DUT gives the RDATA.

I process my standard file in my test and create the data.txt (expected value ) and want to create the queue of class from data.txt (every index will have wdata, address, wr_mask, rd_mask) and based on mask value will create the r_data.

And Finally i will comapare the RDATA (comes from DUT) with expected rdata.

chr_sue · December 2, 2020, 9:22am

In reply to rupeshblr:

The solution would look like this:

int fd;
logic [31:0] addr;
logic [31:0] data;
logic [31:0] wmask;
logic [31:0] rmask;

fd = $fopen ("data.txt" , "r");
// $fscanf returns the number of matches, i.e. 4 in your case
while ($fscanf (fd, "%0h %0h %0h %0h", addr, data, wmask, rmask) == 4) begin
   // do something
end
$fclose(fd);

But using this file solution is not really smart. There is a solution without using the file.

rupeshblr · December 2, 2020, 5:30pm

In reply to chr_sue:
Hi,
Thank you for your reply.
I have written the code but i am not getting the output as per expected result.

module testbech ();
  
class Packet ;
   logic [31:0] addr;
   logic [31:0] data;
   logic [31:0] wmask;
   logic [31:0] rmask;
endclass
  logic [31:0] addr_;
  logic [31:0] data_;
  logic [31:0] wmask_;
  logic [31:0] rmask_;
  
  Packet  qu[$]; 
  int fd;
  
  initial
     begin
       Packet p1;
       p1 = new ;
       fd = $fopen ("data.txt" , "r");
// $fscanf returns the number of matches, i.e. 4 in your case
       while ($fscanf (fd, "%0h %0h %0h %0h", addr_, data_, wmask_, rmask_) == 4) begin
   
        
         p1.addr = addr_;
         p1.data = data_;
         p1.wmask = wmask_;
         p1.rmask = rmask_ ;
         qu.push_back(p1);
         foreach (qu[i])
           begin
             $display ("queue of class [%d] = %h , %h, %h" , i , qu[i].addr, qu[i].data, qu[i].wmask qu[i].rmask);
            end
           p1= new ;
         p1.addr = addr_;
         p1.data = data_;
         p1.wmask = wmask_;
         p1.rmask = rmask_ ;
         //$display ("addr_ %h , data_ %h wmask_ %h , rmask_ %h",p1.addr, p1.data, p1.wmask, p1.rmask);
         qu.push_back(p1);
         foreach (qu[i])
           begin
             $display ("queue of class [%d] = %h , %h, %h" , i , qu[i].addr, qu[i].data, qu[i].wmask  qu[i].rmask);
         
          end
 
end
     $fclose(fd);
end

Output :
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 2] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 3] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 2] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 3] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 4] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 5] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 5] = f000000c , 00000000, 0000ffff
queue of class [ 6] = f000000c , 00000000, 0000ffff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 2] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 3] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 4] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 5] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 6] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 7] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 5] = f000000c , 00000000, 0000ffff
queue of class [ 6] = f000000c , 00000000, 0000ffff
queue of class [ 7] = f0000010 , 0000ffff, 00000000
queue of class [ 8] = f0000010 , 0000ffff, 00000000
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 2] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 3] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 4] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 5] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 6] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 7] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 8] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 9] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 5] = f000000c , 00000000, 0000ffff
queue of class [ 6] = f000000c , 00000000, 0000ffff
queue of class [ 7] = f0000010 , 0000ffff, 00000000
queue of class [ 8] = f0000010 , 0000ffff, 00000000
queue of class [ 9] = f0000014 , 0000aaaa, 00000ff0
queue of class [ 10] = f0000014 , 0000aaaa, 00000ff0
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 2] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 3] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 4] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 5] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 6] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 7] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 8] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 9] = f0000014 , 0000aaaa, 00000ff0 , 000000ff
queue of class [ 10] = f0000014 , 0000aaaa, 00000ff0 , 000000ff
queue of class [ 11] = f0000014 , 0000aaaa, 00000ff0 , 000000ff

Expected Output :- i want queue of class means each index of queue will have all the propties defined in the class (addr, data, wmask, rmask)
queue of class [ 0] = f0000000 , 000FFFF, 000000FF , 000000fF
queue of class [ 1] = f0000004 , 000AAAA, 00000000 , 000000fF
…
…

Data.txt:-
F0000000 FFFF 00FF 00FF
F0000004 AAAA 0000 00FF
F0000008 5555 0000 00FF
F000000c 0000 FFFF 00FF
F0000010 FFFF 0000 00FF
F0000014 AAAA 0FF0 00FF

chr_sue · December 2, 2020, 6:40pm

In reply to rupeshblr:

I’d say your $display is in the wrong place. You should issue the queue content after reading the whole file and not in between.

rupeshblr · December 3, 2020, 5:48am

In reply to chr_sue:
Hi,

After modifying the code, i am still not getting the correct output.

module testbech ();
  
class Packet ;
   
logic [31:0] addr;
logic [31:0] data;
logic [31:0] wmask;
logic [31:0] rmask;
  
  //function new ();
  //endfunction
  
endclass
  
  logic [31:0] addr_;
  logic [31:0] data_;
  logic [31:0] wmask_;
  logic [31:0] rmask_;
  
  Packet  qu[$]; 
  int fd;
  
  initial
     begin
       Packet p1;
       p1 = new ;
       fd = $fopen ("data.txt" , "r");
// $fscanf returns the number of matches, i.e. 4 in your case
       while ($fscanf (fd, "%0h %0h %0h %0h", addr_, data_, wmask_, rmask_) == 4) begin
   
        // $display ("addr %h data %h", addr_, data_);
         p1.addr = addr_;
         p1.data = data_;
         p1.wmask = wmask_;
         p1.rmask = rmask_ ;
         //$display ("addr_ %h , data_ %h wmask_ %h , rmask_ %h",p1.addr, p1.data, p1.wmask, p1.rmask);
         qu.push_back(p1);
         foreach (qu[i])
           begin
             $display ("queue of class [%d] = %h , %h, %h" , i , qu[i].addr, qu[i].data, qu[i].wmask );
         //  $display ("qu %p", qu);
          end
           p1= new ;
          p1.addr = addr_;
         p1.data = data_;
         p1.wmask = wmask_;
         p1.rmask = rmask_ ;
         //$display ("addr_ %h , data_ %h wmask_ %h , rmask_ %h",p1.addr, p1.data, p1.wmask, p1.rmask);
         qu.push_back(p1);
  end
$fclose(fd);
         foreach (qu[i])
           begin
             $display ("queue of class [%d] = %h , %h, %h , %h" , i , qu[i].addr, qu[i].data, qu[i].wmask,  qu[i].rmask);
         
          end
     end  
       
endmodule

Output:
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 5] = f000000c , 00000000, 0000ffff
queue of class [ 6] = f000000c , 00000000, 0000ffff
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 5] = f000000c , 00000000, 0000ffff
queue of class [ 6] = f000000c , 00000000, 0000ffff
queue of class [ 7] = f0000010 , 0000ffff, 00000000
queue of class [ 8] = f0000010 , 0000ffff, 00000000
queue of class [ 0] = f0000000 , 0000ffff, 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000
queue of class [ 2] = f0000004 , 0000aaaa, 00000000
queue of class [ 3] = f0000008 , 00005555, 00000000
queue of class [ 4] = f0000008 , 00005555, 00000000
queue of class [ 5] = f000000c , 00000000, 0000ffff
queue of class [ 6] = f000000c , 00000000, 0000ffff
queue of class [ 7] = f0000010 , 0000ffff, 00000000
queue of class [ 8] = f0000010 , 0000ffff, 00000000
queue of class [ 9] = f0000014 , 0000aaaa, 00000ff0
queue of class [ 10] = f0000014 , 0000aaaa, 00000ff0
queue of class [ 0] = f0000000 , 0000ffff, 000000ff , 000000ff
queue of class [ 1] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 2] = f0000004 , 0000aaaa, 00000000 , 000000ff
queue of class [ 3] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 4] = f0000008 , 00005555, 00000000 , 000000ff
queue of class [ 5] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 6] = f000000c , 00000000, 0000ffff , 000000ff
queue of class [ 7] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 8] = f0000010 , 0000ffff, 00000000 , 000000ff
queue of class [ 9] = f0000014 , 0000aaaa, 00000ff0 , 000000ff
queue of class [ 10] = f0000014 , 0000aaaa, 00000ff0 , 000000ff
queue of class [ 11] = f0000014 , 0000aaaa, 00000ff0 , 000000ff

chr_sue · December 3, 2020, 7:40am

In reply to rupeshblr:

You are still doing wrong things.
See the working code here:

module testbench ();
 
class Packet ;
 
logic [31:0] addr;
logic [31:0] data;
logic [31:0] wmask;
logic [31:0] rmask;
 
  //function new ();
  //endfunction
 
endclass
 
  logic [31:0] addr_;
  logic [31:0] data_;
  logic [31:0] wmask_;
  logic [31:0] rmask_;
 
  Packet  qu[$]; 
  int fd;
  int i = 0;
 
  initial
     begin
       Packet p1;
       fd = $fopen ("data.txt" , "r");
// $fscanf returns the number of matches, i.e. 4 in your case
       while ($fscanf (fd, "%0h %0h %0h %0h", addr_, data_, wmask_, rmask_) == 4) begin
 
         p1 = new ;
         p1.addr = addr_;
         p1.data = data_;
         p1.wmask = wmask_;
         p1.rmask = rmask_ ;
         //$display ("addr_ %h , data_ %h wmask_ %h , rmask_ %h",p1.addr, p1.data, p1.wmask, p1.rmask);
         qu.push_back(p1);
	 $display("qu size = %0d", qu.size);
  end 
$fclose(fd);
         foreach (qu[i])
           begin
             $display ("queue of class [%0d] = %h , %h, %h , %h" , i , qu[i].addr, qu[i].data, qu[i].wmask,  qu[i].rmask);
 
          end
     end  
 
endmodule

rupeshblr · December 10, 2020, 2:16pm

In reply to chr_sue:

I am trying to write the scoreboard code for register wr-rd.

Actual data comes from monitor through uvm_analysis_port.

virtual function void write(svci_rsp_trans_pkt read_rsp);
   `uvm_info("SVCI_MSTR_SEQ","Received read response" , UVM_LOW)
    $display(" vif_rdata = 0x%0x " ,read_rsp.rsp_rdata);
        uvm_info("SCB", $sformatf("Seq_item written from monitor: \n"), UVM_LOW)
        read_rsp.print();
      
        // push captured seq_item into queue
        rcvd_seq_item_q.push_back(read_rsp);
  
  endfunction

Expected data :

task get_all_regs();
  begin
       svci_reg_ svci_reg_h;
        bit [31:0]  addr_;
        bit [63:0]  wdata_; //default data @reset
        bit [63:0]  rdata_; //exp rdata
        bit [63:0]  rmask_; //exp rdata
        bit [63:0]  wmask_; //exp rdata
        int fd;
        int i = 0;
    //call the perl script to parse the ralf file to update queues
    $display ("perl exe");
    $system(" perl /home/rupeshg/REG_SFRtop/datatxtgen.pl  /home/rupeshg/REG_SFRtop/sfr_top_defines.h ");
    fd = $fopen ("data.txt" , "r");
    while ($fscanf (fd, "%0h %0h %0h %0h %h", addr_, wdata_, wmask_, rmask_, rdata_) == 5) begin
 
        svci_reg_h  = new ;
        svci_reg_h.addr = addr_;
        svci_reg_h.wdata = wdata_;
        svci_reg_h.wr_mask = wmask_;
        svci_reg_h.rd_mask = rmask_ ;
        svci_reg_h.rdata = rdata_ ;
         //$display ("addr_ %h , data_ %h wmask_ %h , rmask_ %h",p1.addr, p1.data, p1.wmask, p1.rmask);
         wr_rd_reg_addr_array_q.push_back(svci_reg_h);
	 $display("qu size = %0d", wr_rd_reg_addr_array_q.size);
  end
    $fclose(fd);
         foreach (wr_rd_reg_addr_array_q[i])
           begin
             $display ("queue of class [%0d] = %h , %h, %h , %h, READ_DATA = %h ", i , wr_rd_reg_addr_array_q[i].addr, wr_rd_reg_addr_array_q[i].wdata, wr_rd_reg_addr_array_q[i].wr_mask,  wr_rd_reg_addr_array_q[i].rd_mask, wr_rd_reg_addr_array_q[i].rdata);
 
          end
  end
 
  endtask

Collecting the expected data and actual data :-

virtual task run_phase(uvm_phase phase);
    begin
   // phase.raise_objection(this);
     svci_reg_  exp_pkt ;

     svci_rsp_trans_pkt rcvd_pkt ; 
        //super.run_phase(phase);
      $display ("I am inside scoreboard");
     get_all_regs(); //to do    
        forever begin
            wait(wr_rd_reg_addr_array_q.size() !=0 && rcvd_seq_item_q.size() !=0);
            $display ("I am inside wait");
                exp_pkt = wr_rd_reg_addr_array_q.pop_front();
                rcvd_pkt = rcvd_seq_item_q.pop_front();
                $display("exp_pkt = %p",rcvd_seq_item_q.pop_front() );
                compare_pkt(exp_pkt, rcvd_pkt);                
        end  
     end 
    endtask: run_phase

Compare :-

function void compare_pkt(input svci_reg_ exp_pkt, svci_rsp_trans_pkt  rcvd_pkt);
      if(exp_pkt.ADDR == rcvd_pkt.ADDR) begin
            if(exp_pkt.DATA != rcvd_pkt.DATA) begin
               `uvm_error("DATA MISMATCH ERROR", $sformatf("SCB:: For ADDR: %0h Expecting DATA:%0h but Received DATA: %0h", exp_pkt.ADDR, exp_pkt.DATA, rcvd_pkt.DATA))
         end
      end
      else begin
          `uvm_error("ADDR MISMATCH ERROR", $sformatf("SCB:: Expected ADDR:%0h But received ADDR: %0h", exp_pkt.ADDR, rcvd_pkt.ADDR))      end
    endfunction: compare_pkt

Could anyone suggest me, is it correct or am i missing anything ?

chr_sue · December 10, 2020, 6:54pm

In reply to rupeshblr:

Reading this code does not really help to identify a weakness.
But you are wasting your resources in terms of memory space by writing data to queues. This will slowdown your simulation. You should do a on-the-fly checking of your packet data.
You could store your write data in an associative array in the sequence. This allows data to be stored in a non-contigious way. When reading your data you can pass back the read data as a response to your sequence and compare with the data in the assoc. array.

rupeshblr · December 11, 2020, 5:39am

In reply to chr_sue:

Thanks for suggestion.

Could you suggest some pseudo code for the same if possible

rupeshblr · December 11, 2020, 6:50am

In reply to chr_sue:

In reply to rupeshblr:
The solution would look like this:

int fd;
logic [31:0] addr;
logic [31:0] data;
logic [31:0] wmask;
logic [31:0] rmask;
fd = $fopen ("data.txt" , "r");
// $fscanf returns the number of matches, i.e. 4 in your case
while ($fscanf (fd, "%0h %0h %0h %0h", addr, data, wmask, rmask) == 4) begin
// do something
end
$fclose(fd);

But using this file solution is not really smart. There is a solution without using the file.

May i know the solution without using the file ?

is it the same which you have given in the the last post

"But you are wasting your resources in terms of memory space by writing data to queues. This will slowdown your simulation. You should do a on-the-fly checking of your packet data.
You could store your write data in an associative array in the sequence. This allows data to be stored in a non-contigious way. When reading your data you can pass back the read data as a response to your sequence and compare with the data in the assoc. array. "

chr_sue · December 11, 2020, 8:41am

In reply to rupeshblr:

Could you please show how your sequence (body task) looks like?

rupeshblr · December 11, 2020, 9:46am

In reply to chr_sue:

class svci_master_seq extends svci_base_sequence;

  //Sequence instantiation 
  master_write_cmd_seq	write_seq;
  master_read_cmd_seq	read_seq;
  svci_master_id_pkt	master_id_pkt;
  //int			valid_tag_q[$];
  int		 	j,seq_error_set,valid_tag_q[0:((2**`SVCI_TAG_ID_WIDTH)-1)];

  function new(string name="svci_master_seq");
    super.new(name);
  endfunction

  `uvm_object_utils(svci_master_seq)
  

  virtual task body();
  endtask

  task svci_master_write(bit [31:0] tag='hDEAD,bit [31:0] mid='hDEAD,bit [31:0] addr='hDEAD,
                                 bit [63:0] data='hDEAD,bit [31:0] len='hDEAD,cmd_opc_t opc='hDEAD,
                                 bit [31:0] prty='hDEAD,bit [31:0] delay='hDEAD);

     << Logic >>>
  endtask

  task svci_master_read(bit [31:0] tag='hDEAD,bit [31:0] mid='hDEAD,bit [31:0] addr='hDEAD,bit [31:0] len='hDEAD,cmd_opc_t opc='hDEAD,bit [31:0] prty='hDEAD,bit [31:0] delay='hDEAD);
<<<<logic>>>>>>>>>>>>.     

  endtask

 
endclass : svci_master_seq

class svci_master_reg_seq extends svci_master_seq;

  function new(string name="svci_master_reg_seq");
    super.new(name);
  endfunction

  `uvm_object_utils(svci_master_reg_seq)
  `uvm_declare_p_sequencer(svci_master_sequencer)


  virtual task body();
   reg [63:0] data ;
      for (int i= 0 ; i<= 4; i++)
       begin
         if (i == 0)
         data = 64'hffffffffffffffff;
         else if (i == 1)
         data = 64'hAAAAAAAAAAAAAAAA;
         else if (i == 2)
         data = 64'h5555555555555555;
         else 
         data = 64'h0000000000000000;
  $display ("svci_reg_addr = %h ",`VERSION_ID +`REG_OFFSET );
    svci_master_write(.addr(`VERSION_ID +`REG_OFFSET ), .data(data), .delay('h8), .len('h2), .opc('h2), .mid('h2));
    svci_master_read(.addr(`VERSION_ID +`REG_OFFSET ),  .delay('h8), .len('h2), .opc('h0), .mid('h2));

    $display ("svci_reg_addr = %h ",`IP_FORCE_CG +`REG_OFFSET );
    svci_master_write(.addr(`IP_FORCE_CG +`REG_OFFSET ), .data(data), .delay('h8), .len('h2), .opc('h2), .mid('h2));
    svci_master_read(.addr(`IP_FORCE_CG +`REG_OFFSET ),  .delay('h8), .len('h2), .opc('h0), .mid('h2));

    $display ("svci_reg_addr = %h ",`IP_CG_STATUS +`REG_OFFSET );
    svci_master_write(.addr(`IP_CG_STATUS +`REG_OFFSET ), .data(data), .delay('h8), .len('h2), .opc('h2), .mid('h2));
    svci_master_read(.addr(`IP_CG_STATUS +`REG_OFFSET ),  .delay('h8), .len('h2), .opc('h0), .mid('h2));

  
<<<<<list of all registers>>>>>>>>>>>>>>>

  endtask

endclass : svci_master_reg_seq

chr_sue · December 11, 2020, 10:50am

In reply to rupeshblr:
What I see is you are writing your registers in a fixed ordder with fixed values, even when running in the i-loop. This results in a low verification quality. You should write and read your registers in random order and writing with random values (if random values are possible).
Are the addresses in series or are there gaps in between?
Nevertheless you can put all your register addresses into an adr queue.
Then you are declaring in the body task an associative array. When wrint to the registers you are passing the write data with the corresponding address into an associative array. The associative array contains then the expected data values. When reading the registers you get the read value from the read task. This is the actual value and you can compare with the entry for the corresponding address from the assoc. array. This is a very simple process and avoids any additional scoreboard.
To write the addresses in random order you are calling on the address queue the shuffle method. For reading the registers you are shuffeling again your address queue reading in another random order.

rupeshblr · December 11, 2020, 12:09pm

In reply to chr_sue:
1.Since its SOC level test, I am just checking the walkng 1’s and walking 0’s pattern.
2. Address is in Series Order.

Please provide the pseudo code (template)it will be very helpful. since i am not able to get from above hint.

chr_sue · December 11, 2020, 3:58pm

In reply to rupeshblr:

Please see here. Consider this code as a template.

class my_seq_item extends uvm_sequence_item;
  rand int addr;
  rand logic [63:0]  data;
  rand int   delay;
  rand int   len;
  rand int   opc;
  rand int   mid;

  `uvm_object_utils(my_seq_item)

  function new(string name="my_seq_item");
    super.new(name);
  endfunction

endclass

class svci_master_reg_seq extends svci_master_seq;

int addr_qu[$];                   // address queue
logic [63:0]  expect_mem [int];   // associative array
 
  function new(string name="svci_master_reg_seq");
    super.new(name);
  endfunction
 
  `uvm_object_utils(svci_master_reg_seq)
 // `uvm_declare_p_sequencer(svci_master_sequencer)   // p_sequencer is not a really good idea
 
 
  virtual task body();

     bit [63:0] data;
     my_seq_item item;
     item = my_seq_item::type_id::create("item");

     // fill the addr_queue;
     for (int i = 0; i < no_of_regs; i++)
       addr_queue.push_back(<reg_addresses>);
     addr_queue.shuffle();    // randomize the addresses  

     // Writing all regs
     foreach (addr_queue[i]) begin
       void'(item.randomize() with {addr == addr_queue[i]; delay == 8; len == 2; opc == 2; mid == 2;});
       svci_master_write(.addr(item.addr), .data(item.data), .delay(item.delay), .len(item.len), .opc(item.opc), .mid(item.mid));
       `uvm_info(get_type_name(), $sformatf("writing req addr = %0d with data = %0h ", addr_queue[i], data), UVM_MEDIUM)
       expect_mem[addr_queue[i]] = item.data;
     end   

    // Reading all regs
     addr_queue.shuffle();    // randomize the addresses  
     foreach (addr_queue[i]) begin
       svci_master_read(.addr(addr_queue[i]), .data(data), .delay(`h8), .len(`h2), .opc(`h2), .mid(`h2));
       if (data == expect_mem[addr_queue[i]])
	 `uvm_info(get_type_name(), $sformatf("check passed for addr = %0d", addr_queue[i]), UVM_MEDIUM)  
       else	 
	 `uvm_error(get_type_name(), $sformatf("check failed for addr = %0d", addr_queue[i])
     end	 
 
<<<<<list of all registers>>>>>>>>>>>>>>>
 
  endtask
 
endclass : svci_master_reg_seq

rupeshblr · December 18, 2020, 6:34pm

In reply to chr_sue:

Thanks for template.

with above implementation, I have only problem with Expected data {expect_mem[addr_queue[i]] = item.data;}. the read data coming from design is not equal to data which is randomly generated (item.data). Since i am doing for SOC level verification rd_data is depenent on RD_MASK and WR_MASK and RSTVAL which i have explained on the previous comment

Error :
check failed for addr = f0000000, actual rd_data = 000000000003415e , expected rd_data = af427c75f92dde78.

example :

addr F00003d8 w_data FFFFFFFF wr_mask 0000000F rd_mask 0000000F rd_data 000000000000000F

chr_sue · December 18, 2020, 6:43pm

In reply to rkg_:

It is still unclear to me where the masks are coming from. They should be known also for storing the expected values.

rupeshblr · December 18, 2020, 7:12pm

In reply to chr_sue:

Designers gives the RDF file (where each registers field and value are defined ).

Example
REG ABC : 0x648 {

FIELD	SEL_POL				S_RO	C_RW	0	init=0x0 
							  
								   % 
FIELD	MASK				S_RO	C_RW	15:3	init=0x0  
FIELD	ADDR				S_RO	C_RW	31:19	init=0x0

};
For above register WR_MASk AND RD_MASK will be (THis is the input file for us given by designer)
define ABC_REGRSTVAL 0x0UL
define ABC_REGWRMASK 0xFFF8FFF9UL
define ABC_REGRDMASK 0xFFF8FFF9UL

Now if i give WR_DATA (item.data) 0xFFFFFFFF to abc REG then i will get rd_data (from design) (WR_DATA & REGWRMASK )but as per your implemention expected rd_data will be 0xFFFFFFFF (item.data). so it will give mismatch.

I hope now it is clear