How create function work?

UVM
1 
static function T create(string name, uvm_component parent, ...);
  uvm_object obj;
  uvm_factory f = uvm_factory::get();
  ...
  obj = f.create_component_by_type(get(),contxt,name,parent);
  if (!$cast(create, obj)) begin
    string msg;
    msg = {<"... error message ...">};
    uvm_report_fatal("FCTTYP", msg, UVM_NONE);
  end
endfunction

The above code of create function is taken from uvm_registry class. I have question that how this function works , specially " if (!$cast(create, obj)) begin " I think here create is a function call but when it will be completed. What will create returns ??

2

The use of the function’s name as a return variable comes from legacy Verilog; it had no return statement. You assigned a value to a variable with the same name as the function, and that becomes the return value of the function.

This syntax is one of the reasons SystemVerilog does not have function value chaining, i.e. funct1.funct2.member. Some implementations will allow this as long as it is written as funct1().funct2().member. That way it is unambiguously a chain of function calls, and not variable references.