In reply to ravitejavoora:
First of all, there no reason you can't use `uvm_error in a SystemVerilog directed non-uvm testbench. You can make full use of UVM's reporting mechanism even outside a class based testbench. Most tools make it simple to include the uvm_macros.svh and import the uvm_pkg without have to compile it yourself.
You could even define your own `uvm_error macro so there's no need to include or import.
`define uvm_error(ID,MSG) uvm_pkg::uvm_report_error(ID,MSG);