How to control register adding using Parameter in RAL generation

UVM
1

Hi,

In our design few registers are controlled using different design parameters.
For example FEW registers will be present only if particular parameter of the design is enabled.

How do I take care of these while generating RAL file ? I want those registers to add if that parameter is enabled

Example:
if ( PARAM1_EN ==1 )
this.default_map.add_reg(this.REG1, `UVM_REG_ADDR_WIDTH’h0, “RW”, 0);

2

In reply to kpkrishna:

I would expect that this may be a feature of the tool you use to generate a RAL file. You would need to refer to your tool documentation to see if this is supported.

You could possibly hand edit the generated file as well.

In reality, what does it matter if there are additional registers in the RAL file that don’t exist in the design? As long as you don’t access these registers, there will be no side effects. You may run into issues if you do some random register accesses, but your design should still return values, albeit they may not be valid data.