In reply to chr_sue:
When the whole chip is in netlist, it takes many minutes to compile the whole design.
At the moment, we do not have uvm code in the testbench yet. We are doing experiment
to see what uvm can bring to improve our verification.
The 3 flash interfaces are dut_flash_if, flash1_if, flash2_if.
How can we dynamically connect dut_flash_if to flash1_if in test1,
connect dut_flash_if to flash2_if in test2....?
The flash data is bidirectional. Using multiplexer in the testbench needs to refer to
the direction control signals in the DUT or in the flash model and might give timing problem
for netlist simulation. We would like to avoid the multiplexer in the testbench if possible.
At the moment we did the following definition,
In the staic part of the testbench,
The DUT has a flash interface, dut_flash_if
The FLASH1 verilog model has a flash interface, falsh1_if.
The FLASH2 verilog model has a flash interface, flash2_if.
In the dynamic part,
I defined 3 virtual interface in the uvm agent, dut_flash_vif, flash1_vif, flash2_vif.
By using uvm_config_db, we connect dut_flash_vif to dut_flash_if, flash1_vif to falsh1_if, flash2_vif to flash2_if. How can we dynamically connect dut_flash_vif to flash1_vif in test1,
connect dut_flash_vif to flash2_vif in test2....?
Is the explanation of our requirement clear?