Hi sir,
I am beginner of the UVM. So i am tried to model a AND GATE OPERATION in uvm.
But i am faced the run time error in “Instantiation of ‘mem_intf’ failed. The design unit was not found”.
my code is below
import uvm_pkg::*;
`include “uvm_macros.svh”
class and_seq_item extends uvm_sequence_item;
rand bit a;
rand bit b;
rand bit out;
uvm_object_utils_begin(and_seq_item) uvm_field_int(a,UVM_ALL_ON)
uvm_field_int(b,UVM_ALL_ON) uvm_field_int(out,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name="and_seq_item");
super.new(name);
endfunction
constraint aa{a;b;}
endclass
class and_sequence extends uvm_sequence#(and_seq_item);
`uvm_object_utils(and_sequence)
function new(string name=“and_sequence”);
super.new(name);
endfunction
virtual task body();
req=and_seq_item::type_id::create(“req”,this);
wait_for_grand();
req.randomize();
send_request(req);
wait_for_item_done();
get_response(rsp);
/*
`uvm_do_with(reg,{a==(0||1); b==(0||1);})
*/
endtask
endclass
class and_sequencer extends uvm_sequencer#(and_seq_item);
`uvm_component_utils(and_sequencer)
function new(string name=“and_sequencer”, uvm_component parent=null);
super.new(name,parent);
endfunction
endclass
class and_driver extends uvm_driver#(and_seq_item);
virtual mem_intf vif;
`uvm_component_utils(and_driver)
function new(string name=“and_driver”,uvm_component parent =null);
super.new (name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual mem_if)::get(this, “”, “vif”, vif))
`uvm_fatal(“NO_VIF”,{“virtual interface must be set for: “,get_full_name(),”.vif”});
endfunction
task run_phase(uvm_phase phase);
and_seq_item_port.get_next_item(req);
drive();
and_seq_item_port.item_done();
endtask
task drive();
repeat(4)
begin
req.printt();
vif.a=req.a;
vif.b=req.b;
vif.out=req.out;
output_logic();
#5;
end
endtask
task output_logic();
if(vif.a && vif.b)
begin
vif.out=1;
$display("a=%d b=%d out=%d",vif.a,vif.b,vif.out);
end
else
begin
vif.out=0;
$display("a=%d b=%d out=%d",vif.a,vif.b,vif.out);
end
endtask
endclass
class and_agent extends uvm_agent;
and_driver driver;
and_sequencer sequencer;
`uvm_component_utils(and_agent)
function new(string name=“and_agent”, uvm_component parent=null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver=and_driver::type_id::create(“driver”,this);
sequencer=and_sequencer::type_id::create(“sequencer”,this);
endfunction
function void connect_phase(uvm_phase phase);
driver.and_seq_item_port.connect(sequencer.and_seq_item_export);
endfunction
endclass
class and_env extends uvm_env;
and_agent agent;
`uvm_component_utils(and_env)
function new(string name=“”,uvm_component parent =null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent=and_agent::type_id::create(“agent”,this);
endfunction
endclass
class and_test extends uvm_env;
and_env env;
and_sequence seq;
`uvm_component_utils(and_test)
function new (string name=“test”,uvm_component parent=null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env=and_env::type_id::create(“env”,this);
seq=and_sequence::type_id::create(“seq”,this);
endfunction
virtual task run_phase(uvm_phase phase);
seq.start(env.agent.sequencer);
endtask
endclass
module top;
bit clock;
initial begin
forever begin
#10 clock=~clock;
end
end
mem_intf vif();
memoryy dut(.clock(intf.clock),.a(intf.a),.b(intf.b),.out(intf.out));
initial begin
uvm_config_db#(virtual mem_if)::set(uvm_root::get(),“*”,“mem_intf”,vif);
run_test();
end
endmodule