As I coded the scoreboard as follows :
class scoreboard extends uvm_scoreboard;
`uvm_component_utils(scoreboard)
int no_of_compared_txns;
read_txn sb_rd_txn;
write_txn sb_wr_txn;
bit [7:0]ram_model[int];
uvm_analysis_export #(read_txn)item_collected_export_rd_txn;
uvm_analysis_export #(write_txn)item_collected_export_wr_txn;
uvm_tlm_analysis_fifo #(read_txn)rd_fifo;
uvm_tlm_analysis_fifo #(write_txn)wr_fifo;
//new constructor
function new (string name, uvm_component parent);
super.new(name, parent);
sb_rd_txn=read_txn::type_id::create("sb_rd_txn");
sb_wr_txn=write_txn::type_id::create("sb_wr_txn");
endfunction : new
//Building
function void build_phase(uvm_phase phase);
super.build_phase(phase);
item_collected_export_rd_txn= new("item_collected_export_rd_txn", this);
item_collected_export_wr_txn= new("item_collected_export_wr_txn", this);
rd_fifo=new("rd_fifo",this);
wr_fifo=new("wr_fifo",this);
endfunction: build_phase
//connect phase
function void connect_phase(uvm_phase phase);
item_collected_export_rd_txn.connect(rd_fifo.analysis_export);
item_collected_export_wr_txn.connect(wr_fifo.analysis_export);
endfunction
task run_phase(uvm_phase phase);
forever begin
wr_fifo.get(sb_wr_txn);
write();
rd_fifo.get(sb_rd_txn);
compare();
end
endtask
virtual function void write();
//if((!sb_wr_txn.csn_0)||(!sb_wr_txn.csn_1)) begin
fork
if(sb_wr_txn.wen_0)
ram_model[sb_wr_txn.addr_0]=sb_wr_txn.datain_0;
if(sb_wr_txn.wen_1)
ram_model[sb_wr_txn.addr_1]=sb_wr_txn.datain_1;
join
//end
endfunction
virtual function void compare();
if(sb_rd_txn.ren_0) begin
if(ram_model.exists(sb_rd_txn.addr_0))begin
if((ram_model [sb_rd_txn.addr_0]==sb_rd_txn.dataout_0)||(ram_model [sb_rd_txn.addr_0]==sb_rd_txn.dataout_1)) begin
`uvm_info("compare", {"Test: OK!"}, UVM_LOW);
$display("\n In port_0 & detection correct");
$display("scoreboard:: addr_0=%0d dataout_0=%0d datain_0=%0d \n",sb_rd_txn.addr_0,sb_rd_txn.dataout_0,ram_model[sb_rd_txn.addr_0]);
no_of_compared_txns++;
end
else begin
`uvm_info("compare", {"Test: Fail!"}, UVM_LOW);
$display("\n scoreboard:: addr_0=%d,actual data=%d,expected data=%0d",sb_rd_txn.addr_0,sb_rd_txn.dataout_0,ram_model[sb_rd_txn.addr_0]);
$error(" Data Mismatch\n");
end
end
end
if(sb_rd_txn.ren_1) begin
if(ram_model.exists(sb_rd_txn.addr_1))begin
if((ram_model [sb_rd_txn.addr_1]==sb_rd_txn.dataout_1)||(ram_model [sb_rd_txn.addr_1]==sb_rd_txn.dataout_0)) begin
`uvm_info("compare", {"Test: OK!"}, UVM_LOW);
$display("\n In port_1 & detection correct");
$display("scoreboard:: addr_1=%d dataout_1=%d expected data=%0d\n",sb_rd_txn.addr_1,sb_rd_txn.dataout_1,ram_model[sb_rd_txn.addr_1]);
no_of_compared_txns++;
end
else begin
`uvm_info("compare", {"Test: Fail!"}, UVM_LOW);
$display("\n scoreboard:: addr_1=%d,actual data=%d,expected data=%0d",sb_rd_txn.addr_1,sb_rd_txn.dataout_1,ram_model[sb_rd_txn.addr_1]);
$error(" Data Mismatch\n");
end
end
end
endfunction
endclass
But after simulation I find only four data checks have completed. Is my ran_phase task is wrong or I need to change my compare logic. It is the scoreboard of a dual port ram.