Hi,
I would like to know if possible from "uvm testcase" class to have a path back to the DUT submodules in order to switch off assertions. Because assertions are based on sub-module of DUT, the goal is to switch off assertion depends on the test.
DUT module:
module dut_module(
input wire clk,
input wire reset,
...);
example_module example_module_u
(
.example_clk (clk),
.example_count (count),
.example_enable (enable),
.example_ack (ack)
);
endmodule;
//assertion module
module ust_example_assertions #(parameter parameter1)(
//port declartion for the example module
input wire example_clk,
input wire [parameter1-1:0] example_count,
input wire example_enable,
input wire example_ack);
assert_name: assert property(@(posedge example_clk)!(example_enable && example_ack && example_count > 17'h0_1000))
else
$fatal(1,"FATAL: This transaction is invalid in %m at %0d ps.", $time);
endmodule:ust_example_assertions
//testbench top:
Bind example_module example_assertions#(.parameter1(parameter1)) inst_assert(.*);
//uvm testcase
class example_test extends uvm_test;
...
task run_phase(uvm_phase phase)
$assertoff(1, path to the DUT submodule) //something similar
endtask
endclass
Thanks,
Chao
