How to check the module was reset by reading/writing registers?

UVM
,
1

Hi,

Can someone please help me how to check the module was reset by reading/writing registers?
Thank you.

-Sruthi.

2

In reply to sruthikrapa:

Can someone please help me how to check the module was reset by reading/writing registers?

Have you considered assertions?


  int a, b; 
  bit clk, c, d, reset_n; 
  initial begin // use initial if upon boot. 
    @(posedge reset_n) 
    a_abcd: assert (a==0 && b==0 && c==0 && d==0); // check when reset_n is deactivated 
  end

  // if reset_n can occur during a simulation run 
  // use a concurrent assertion 
  ap_resetn: assert property(@(posedge reset_n) // when reset_n is deactivated 
           a==0 && b==0 && c==0 && d==0 );  

  ap_at_resetn: assert property(@(posedge clk) // assuming synchronous reset
              reset_n==0)  |=>   a==0 && b==0 && c==0 && d==0); // change is at next cycle

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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