Hi,
I am trying to know how interrupts are handled in UVM and I got the below question.
how to check if an interrupt was generated?
Can someone please help me out.
Thanks,
Sruthi.
In reply to sruthikrapa:
I am trying to know how interrupts are handled in UVM and I got the below question.
how to check if an interrupt was generated?
How to check if an interrupt was generated?
What is an interrupt? It is generally a response by an interface that something happened and now there is a need for the cpu to do something. For example, the completion of the receipt of a message should cause an interrupt.
SO how do you detect that an interrupt is generated? My preferred approach is through an assertion, which can be implemented in SVA, tasks, or UVM.
In UVM, you have the monitor and scoreboard that do the detection and verification of interface activities. FOr tasks an assertion, see
Abstract: Understanding the engine behind SVA provides not only a better appreciation and limitations of SVA, but in some situations provide features that cannot be simply implemented with the current definition of SVA. This paper first explains, by example, how a relatively simple assertion example can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as an error in the assertion. The paper then provides examples that uses computational variables within threads; those variables can cause, in some cases, errors in SVA. The strictly emulation model with tasks solves this issue.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
See the interrupt examples in the code examples
https://verificationacademy.com/cookbook/cookbook-code-examples