I’d like to ask a question how to change RTL signals during the simulation in our TB ?
Usually we will force some of signals (most of them are input for our DUT) in the top like below.
module top;
...
initial begin
force tb.core.input1 = 1'b0;
force tb.core.input2 = 2'b00;
...
end
But I need to change some of signals several times during the simulation. How to do that ?