How can we know which statements actually take simulation time in uvm or system verilog?

UVM
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How can we know which statements actually take simulation time in uvm or system verilog ?

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In reply to jaswanth_b:

This can be done profiling your code in the simulator. A profiler determine CPU/memory usage during a simulation run.

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In reply to jaswanth_b:

From other posts, you need to clarify what you mean by “simulation time”. Do you mean the amount of CPU the host simulation tool consumes, or do you mean the time you are trying to model?

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In reply to dave_59:

In reply to jaswanth_b:
From other posts, you need to clarify what you mean by “simulation time”. Do you mean the amount of CPU the host simulation tool consumes, or do you mean the time you are trying to model?

I mean the time you are trying to model.

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In reply to jaswanth_b:
You can assume anything defined as a task could consume time, and anything defined as a function does not.